Design theory and fabrication process integration of 32nm node Si, Ge and Si1-xGex vertical dual carrier field effect transistor SOC for switching and communication applications

Abstract

With the announcement of Intel and IBM to provide 45 nm CPUs, the semiconductor industry has been engaged in the research and development work of 32 nm node CMOS technology. In this paper, we present our development work on the design theory and fabrication process integration of 32 nm node Ge, Si and Si_1-xGe_x "vertical dual carrier field effect transistor" (VDCFET) ASIC for switching and small signal communication applications. The effective channel length of our 32 nm node Ge, Si and Si_1-xGe_x switching VDCFET have been reduced to 9 nm. The effective channel length of our 32 nm node Ge, Si and Si_1-xGe_x communication small signal VDCFET has been reduced to 5 nm. The merits of these Ge, Si and Si_1-xGe_x 32 nm node VDCFET shall be compared.