{"title":"A Simplified Flop MTBF Extraction Methodology","authors":"Ang Boon Chong, Aw Kean Hong","doi":"10.1109/iccss55260.2022.9802161","DOIUrl":null,"url":null,"abstract":"When asynchronous data is registered by a clocked flop, there is a probability of metastability failure. In applications such as synchronization or data recovery, the circuit is susceptible to metastability failure due to the asynchronous nature of the data input to the flop. As the performance of chip increases with shrinking technology node as well as increasing complexity of the clock network of the chip to cater for multiple clock domains transfer, the mean time between failure (MTBF) requirement for a metaharden flops is getting higher and tougher to meet. Metaharden flops design involves tradeoff between flop mean time between failure (MTBF) requirement with the flip-flop’s area, power, and performance. This paper will share a simplified flop’s mean time between failure (MTBF) extraction methodology that will reduce the pessimism in the flop’s MTBF derivation and the flop’s MTBF extraction effort. Hopefully, audience will benefit from the sharing.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iccss55260.2022.9802161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
When asynchronous data is registered by a clocked flop, there is a probability of metastability failure. In applications such as synchronization or data recovery, the circuit is susceptible to metastability failure due to the asynchronous nature of the data input to the flop. As the performance of chip increases with shrinking technology node as well as increasing complexity of the clock network of the chip to cater for multiple clock domains transfer, the mean time between failure (MTBF) requirement for a metaharden flops is getting higher and tougher to meet. Metaharden flops design involves tradeoff between flop mean time between failure (MTBF) requirement with the flip-flop’s area, power, and performance. This paper will share a simplified flop’s mean time between failure (MTBF) extraction methodology that will reduce the pessimism in the flop’s MTBF derivation and the flop’s MTBF extraction effort. Hopefully, audience will benefit from the sharing.