Efficient wireless Digital Up Converters design using system generator

Abstract

A WCDMA Digital Up Converter (DUC) design based on FPGA is presented. Aiming to shorten the design period and increase the design performance, a powerful design tool, Xilinx System Generator is used. The RRC filter and the Half-band filter are designed by using MATLAB FDATool, and implemented by using Xilinx FIR Compiler. The DDS module is generated by Xilinx DDS Compiler. Finally, the DUC design is implemented into Xilinx XC5VSX50T device. Using Vitex-5 DSP48E slices, the complex-multiplier speed reaches 368.64 MHz. The simulation results show that the system design flow based on Xilinx System Generator is simple and feasible, and the productivity is increased. The performance meets the requirements for the downlink transmit path.