UVM based approaches to functional verification of communication controllers of microprocessor systems

Abstract

The approach to functional verification of communication controllers based on developing layered UVM test systems is considered in this paper. Some benefits of application standalone simulation based verification are marked out. The architecture most of communication controllers could be divided into three logical layers: the transport layer, the channel layer and the physical layer. The main features and functions of the communication controller's layers are described. We proposed the approach which lies in developing one UVM test system and one design under test (DUT) consisting of controllers of each layer. Some novel techniques for checking the correctness of communication controller implementation at all layers are proposed and used. The architecture of the UVM-based test system and functions of its components are presented.