Inter-signal timing skew compensation of parallel links with current-mode incremental signaling

Abstract

This paper proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signaling. The proposed current-mode receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values for convenient phase comparison. The feedback at the front-end of the receiver minimizes the dependence of the input impedance of the receiver on the direction of the channel current so that signal-dependent impedance mismatch is minimized. Inter-signal timing skew is compensated by inserting a delay line for each channel so that a single sampling clock is needed for all channels. A 2-bit 1 Gbytes/s parallel link has been implemented in UMC-0.13 mum 1.2V CMOS technology and analyzed using SpectreRF with BSIM3V3 device models. Simulation results show that inter-signal timing skews can be effectively compensated using the proposed deskewing scheme.