Pub Date : 2008-12-08DOI: 10.1109/ICOSP.2008.4697698
M. Akhtar, W. Mitsuhashi
The paper concerns active control of impulsive noise. The most famous filtered-x least mean square (FxLMS) algorithm for active noise control (ANC) systems is based on the minimization of variance of mean-squared-error signal. The impulsive noise can be modeled using non-Gaussian stable process for which second order moments do not exist. The FxLMS algorithm, therefore, becomes unstable for the impulsive noise. Among the existing algorithms for ANC of impulsive noise, one is based on the minimizing least mean p-power (LMP) of the error signal, resulting in FxLMP algorithm. The other is based on modifying; on the basis of statistics properties; the reference signal in the update equation of the FxLMS algorithm. In this paper, the proposed algorithm is an extension of the later approach. Extensive simulations are carried out, which demonstrate the effectiveness of the proposed algorithm. It achieves the best performance among the existing algorithms, and at the same computational complexity as that of FxLMS algorithm.
{"title":"Improved adaptive algorithm for active noise control of impulsive noise","authors":"M. Akhtar, W. Mitsuhashi","doi":"10.1109/ICOSP.2008.4697698","DOIUrl":"https://doi.org/10.1109/ICOSP.2008.4697698","url":null,"abstract":"The paper concerns active control of impulsive noise. The most famous filtered-x least mean square (FxLMS) algorithm for active noise control (ANC) systems is based on the minimization of variance of mean-squared-error signal. The impulsive noise can be modeled using non-Gaussian stable process for which second order moments do not exist. The FxLMS algorithm, therefore, becomes unstable for the impulsive noise. Among the existing algorithms for ANC of impulsive noise, one is based on the minimizing least mean p-power (LMP) of the error signal, resulting in FxLMP algorithm. The other is based on modifying; on the basis of statistics properties; the reference signal in the update equation of the FxLMS algorithm. In this paper, the proposed algorithm is an extension of the later approach. Extensive simulations are carried out, which demonstrate the effectiveness of the proposed algorithm. It achieves the best performance among the existing algorithms, and at the same computational complexity as that of FxLMS algorithm.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128101188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-05DOI: 10.1109/MWSCAS.2008.4616850
H. Saleh, E. Swartzlander
A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45 nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.
{"title":"A floating-point fused add-subtract unit","authors":"H. Saleh, E. Swartzlander","doi":"10.1109/MWSCAS.2008.4616850","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616850","url":null,"abstract":"A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45 nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123862172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616954
S. Fattah, W. Zhu, M. Ahmad
This paper presents an identification technique for minimum-phase autoregressive (AR) systems using noise-corrupted observations. In order to reduce the effect of noise in the correlation domain, instead of using the conventional autocorrelation function (ACF), a once-repeated ACF (ORACF) of noisy observations has been employed. Based on characteristics of the ORACF under a noisy condition, a set of equations has been developed. The AR parameters are estimated by solving these equations in the form of a quadratic eigenvalue problem. Computer simulations are carried out for AR systems of different orders under noisy environments showing a superior identification performance in terms of estimation accuracy and consistency.
{"title":"A correlation domain algorithm for autoregressive system identification from noisy observations","authors":"S. Fattah, W. Zhu, M. Ahmad","doi":"10.1109/MWSCAS.2008.4616954","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616954","url":null,"abstract":"This paper presents an identification technique for minimum-phase autoregressive (AR) systems using noise-corrupted observations. In order to reduce the effect of noise in the correlation domain, instead of using the conventional autocorrelation function (ACF), a once-repeated ACF (ORACF) of noisy observations has been employed. Based on characteristics of the ORACF under a noisy condition, a set of equations has been developed. The AR parameters are estimated by solving these equations in the form of a quadratic eigenvalue problem. Computer simulations are carried out for AR systems of different orders under noisy environments showing a superior identification performance in terms of estimation accuracy and consistency.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115296911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616865
Chul Kim, T. Lehmann, S. Nooshabadi
A novel all-digital ultra-wideband pulse generator (PG) with pulse tuning capability has been implemented in a standard 0.18 muCMOS process with ultra low dynamic energy consumption of 15 pJ per pulse with no static current flow at 200 MHz pulse repetition frequency (PRF) and 1.8 V power supply. The PG generates bi-phase Gaussian, plus its 1st and 5th derivatives with a tunable pulse width, amplitude and transmit (Tx) power, using a simple circuitry, through a precise timing control of H-bridge output stage. All-digital architecture allows easy integration into a standard CMOS process.
{"title":"A 15pJ/pulse all-digital UWB pulse generator with pulse tuning capability","authors":"Chul Kim, T. Lehmann, S. Nooshabadi","doi":"10.1109/MWSCAS.2008.4616865","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616865","url":null,"abstract":"A novel all-digital ultra-wideband pulse generator (PG) with pulse tuning capability has been implemented in a standard 0.18 muCMOS process with ultra low dynamic energy consumption of 15 pJ per pulse with no static current flow at 200 MHz pulse repetition frequency (PRF) and 1.8 V power supply. The PG generates bi-phase Gaussian, plus its 1st and 5th derivatives with a tunable pulse width, amplitude and transmit (Tx) power, using a simple circuitry, through a precise timing control of H-bridge output stage. All-digital architecture allows easy integration into a standard CMOS process.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115611415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616779
H. Lo, H. Yoo, D.V. Anderson
This paper presents a new hardware efficient distributed arithmetic (DA) architecture for high order (> 1024) digital filters. The new architecture is termed reusable distributed arithmetic (RDA). The proposed architecture has a linear dependence of memory size on filter length versus the exponential dependence found in lookup table (LUT)-based designs by removing the LUT and generating the required combinations online. In addition, the proposed RDA architecture reuses the computation blocks much like the way multipliers are reused in multiplier-based architectures to reduce hardware complexity. The proposed RDA design is compared against a multiplier-based (MM) design to illustrate the area dependency of both designs on filter length. FPGA synthesis results confirm that the RDA design is capable of much higher order filters (2048 tap) than the MM design (512 tap) while at the same time having similar equivalent gate counts and throughput.
{"title":"A reusable distributed arithmetic architecture for FIR filtering","authors":"H. Lo, H. Yoo, D.V. Anderson","doi":"10.1109/MWSCAS.2008.4616779","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616779","url":null,"abstract":"This paper presents a new hardware efficient distributed arithmetic (DA) architecture for high order (> 1024) digital filters. The new architecture is termed reusable distributed arithmetic (RDA). The proposed architecture has a linear dependence of memory size on filter length versus the exponential dependence found in lookup table (LUT)-based designs by removing the LUT and generating the required combinations online. In addition, the proposed RDA architecture reuses the computation blocks much like the way multipliers are reused in multiplier-based architectures to reduce hardware complexity. The proposed RDA design is compared against a multiplier-based (MM) design to illustrate the area dependency of both designs on filter length. FPGA synthesis results confirm that the RDA design is capable of much higher order filters (2048 tap) than the MM design (512 tap) while at the same time having similar equivalent gate counts and throughput.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123129468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616872
S. Kurtas, B. Taskin
Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution functions (PDFs) rather than deterministically, have emerged to more accurately portray integrated circuit performance. This analysis has been thoroughly performed on traditional zero clock skew circuits where the synchronizing clock signal is assumed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling (CSS) imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3sigma variation), SST is observed to improve the accuracy of measurement, thereby increasing the average clock period improvement to 38.25% as compared to zero clock skew circuits.
{"title":"Statistical timing analysis of nonzero clock skew circuits","authors":"S. Kurtas, B. Taskin","doi":"10.1109/MWSCAS.2008.4616872","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616872","url":null,"abstract":"Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution functions (PDFs) rather than deterministically, have emerged to more accurately portray integrated circuit performance. This analysis has been thoroughly performed on traditional zero clock skew circuits where the synchronizing clock signal is assumed to arrive in phase with respect to each register. However, designers will often schedule the clock skew to different registers in order to decrease the minimum clock period of the entire circuit. Clock skew scheduling (CSS) imparts very different timing constraints that are based, in part, on the topology of the circuit. In this paper, SSTA is applied to nonzero clock skew circuits in order to determine the accuracy improvement relative to their zero skew counterparts, and also to assess how the results of skew scheduling might be impacted with more accurate statistical modeling. For 99.7% timing yield (3sigma variation), SST is observed to improve the accuracy of measurement, thereby increasing the average clock period improvement to 38.25% as compared to zero clock skew circuits.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123155766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616903
Changxu Du, Yici Cai, Xianlong Hong
The phase of resource allocation is always ignored in analog routers, since the small scale of analog integrated circuits does not require it. However, in this paper, we introduce a novel resource allocation algorithm, for the traditional greedy strategy without resource allocation cannot meet many performance requirements of analog integrated circuits at all. This algorithm is based on the probabilistic model, considering the important performance requirements, such as variable wire widths, matching, and sensitivity, of analog integrated circuits. Factors about performance are involved in the routing phase in advance, by contrast to the traditional approaches that pay only attention to the wire congestion. Experimental results demonstrate that the routability of nets, especially critical nets, is improved, and the wire congestion in different metal layers is manipulated well, with the guarantee of much significant performance.
{"title":"A performance driven probabilistic resource allocation algorithm for analog routers","authors":"Changxu Du, Yici Cai, Xianlong Hong","doi":"10.1109/MWSCAS.2008.4616903","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616903","url":null,"abstract":"The phase of resource allocation is always ignored in analog routers, since the small scale of analog integrated circuits does not require it. However, in this paper, we introduce a novel resource allocation algorithm, for the traditional greedy strategy without resource allocation cannot meet many performance requirements of analog integrated circuits at all. This algorithm is based on the probabilistic model, considering the important performance requirements, such as variable wire widths, matching, and sensitivity, of analog integrated circuits. Factors about performance are involved in the routing phase in advance, by contrast to the traditional approaches that pay only attention to the wire congestion. Experimental results demonstrate that the routability of nets, especially critical nets, is improved, and the wire congestion in different metal layers is manipulated well, with the guarantee of much significant performance.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121806561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616874
Lubomir Ivanov
We present an algorithm for automatic generation of behavioral models of non-iterated systems from a structural Verilog specification. The models are represented as Chu spaces over the set of system events, and are used for verifying system behavior. The correctness and time complexity of the presented algorithm are briefly discussed along with a small example.
{"title":"Automatic generation of Chu space model expressions for verification","authors":"Lubomir Ivanov","doi":"10.1109/MWSCAS.2008.4616874","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616874","url":null,"abstract":"We present an algorithm for automatic generation of behavioral models of non-iterated systems from a structural Verilog specification. The models are represented as Chu spaces over the set of system events, and are used for verifying system behavior. The correctness and time complexity of the presented algorithm are briefly discussed along with a small example.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115751658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616727
B. Rumberg, Kyle McMillan, Charles Rea, David W. Graham
Drawing inspiration from biological studies, we have developed a novel silicon cochlea model which better accounts for the effect of local fluid coupling on the basilar membrane. This fluid coupling is emulated by coupling an extra wideband filter to each narrowband filter in the array. In this paper we present some of the biological background and give a short survey of earlier silicon cochlea models. We then briefly discuss the bandpass-filter element used in the circuit before presenting our silicon cochlea model along with measurements of the performance of a single filter tap.
{"title":"Lateral coupling in silicon cochlear models","authors":"B. Rumberg, Kyle McMillan, Charles Rea, David W. Graham","doi":"10.1109/MWSCAS.2008.4616727","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616727","url":null,"abstract":"Drawing inspiration from biological studies, we have developed a novel silicon cochlea model which better accounts for the effect of local fluid coupling on the basilar membrane. This fluid coupling is emulated by coupling an extra wideband filter to each narrowband filter in the array. In this paper we present some of the biological background and give a short survey of earlier silicon cochlea models. We then briefly discuss the bandpass-filter element used in the circuit before presenting our silicon cochlea model along with measurements of the performance of a single filter tap.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116802726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-03DOI: 10.1109/MWSCAS.2008.4616780
M. Abdelwahab, W. Mikhael
Recently, due to emerging critical applications such as biomedical, and security applications, the area of intelligent signal processing has been receiving considerable attention. In this contribution, we present an intelligent signal processing system applied to signal recognition and classification. The system employs different structures, multicriteria and multitransform techniques. In addition, principal component analysis in the transform domain in conjunction with vector quantization is developed which result in further improvement in the recognition accuracy and dimensionality reduction. Experimental results are given which confirm the excellent properties of the proposed approaches.
{"title":"Parallel structure system employing PCA and VQ in the transform domain for facial recognition","authors":"M. Abdelwahab, W. Mikhael","doi":"10.1109/MWSCAS.2008.4616780","DOIUrl":"https://doi.org/10.1109/MWSCAS.2008.4616780","url":null,"abstract":"Recently, due to emerging critical applications such as biomedical, and security applications, the area of intelligent signal processing has been receiving considerable attention. In this contribution, we present an intelligent signal processing system applied to signal recognition and classification. The system employs different structures, multicriteria and multitransform techniques. In addition, principal component analysis in the transform domain in conjunction with vector quantization is developed which result in further improvement in the recognition accuracy and dimensionality reduction. Experimental results are given which confirm the excellent properties of the proposed approaches.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117201561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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