A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS

Sushrant Monga, Vinod Kumar
{"title":"A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS","authors":"Sushrant Monga, Vinod Kumar","doi":"10.1109/ESSCIRC.2011.6044896","DOIUrl":null,"url":null,"abstract":"Architecture for I/O driver is proposed for high voltage (up to 3.6V) application by using low voltage devices. The proposed I/O is configurable to support multi supply range (1.8V-2.7V-3.6V). The buffer is designed in 40nm CMOS process by using standard 32Å oxide devices. This technique generates a set of dynamic bias signals as a function of input data sequence and the present value of the output which are fed to the cascoded stages to derive the next state of the output PAD. The experimental results confirmed successful operation up to 200 MHz with 10pF load on IO pad, with multiple supply rails.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2011.6044896","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

Architecture for I/O driver is proposed for high voltage (up to 3.6V) application by using low voltage devices. The proposed I/O is configurable to support multi supply range (1.8V-2.7V-3.6V). The buffer is designed in 40nm CMOS process by using standard 32Å oxide devices. This technique generates a set of dynamic bias signals as a function of input data sequence and the present value of the output which are fed to the cascoded stages to derive the next state of the output PAD. The experimental results confirmed successful operation up to 200 MHz with 10pF load on IO pad, with multiple supply rails.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
一个73μW 400Mbps耐压1.8V-3.6V 40nm CMOS驱动器
通过使用低压器件,提出了用于高电压(高达3.6V)应用的I/O驱动架构。建议的I/O可配置以支持多电源范围(1.8V-2.7V-3.6V)。该缓冲器采用40nm CMOS工艺设计,采用标准32Å氧化物器件。该技术产生一组动态偏置信号,作为输入数据序列和输出值的函数,这些信号被馈送到级联编码阶段,以导出输出PAD的下一个状态。实验结果证实,在IO衬垫上,使用多个电源轨,在高达200 MHz的10pF负载下成功运行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A precision DTMOST-based temperature sensor 8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1