Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044919
Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee
Due to the increasing uncertainty of data for higher transmission rate, the Forward Error Correction (FEC) devices need to provide more powerful error correcting capability for optical communication systems. As compared with traditional hard RS decoders, the soft RS decoders can perform substantial coding gain but require much higher hardware complexity. In this paper, a decision-confined algorithm is proposed to enhance the error correcting performance with an area-efficient architecture. The novelty is that, instead of decoding numerous possible transmitted codewords and choosing the most likely one, only one candidate sequence will be decoded after confining the degree of error-locator polynomial Λ(x). For RS (255,239) codes, simulation results confirm that our approach provides 0.4 dB performance gain at 104 CER over the hard RS decoders. The experimental result reveals that our soft decoder can achieve 2.56 Gb/s throughput in standard CMOS 90 nm technology while having similar complexity as a hard decoder. It can fit well for 10–40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.
{"title":"A 2.56 Gb/s soft RS (255,239) decoder chip for optical communication systems","authors":"Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ESSCIRC.2011.6044919","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044919","url":null,"abstract":"Due to the increasing uncertainty of data for higher transmission rate, the Forward Error Correction (FEC) devices need to provide more powerful error correcting capability for optical communication systems. As compared with traditional hard RS decoders, the soft RS decoders can perform substantial coding gain but require much higher hardware complexity. In this paper, a decision-confined algorithm is proposed to enhance the error correcting performance with an area-efficient architecture. The novelty is that, instead of decoding numerous possible transmitted codewords and choosing the most likely one, only one candidate sequence will be decoded after confining the degree of error-locator polynomial Λ(x). For RS (255,239) codes, simulation results confirm that our approach provides 0.4 dB performance gain at 104 CER over the hard RS decoders. The experimental result reveals that our soft decoder can achieve 2.56 Gb/s throughput in standard CMOS 90 nm technology while having similar complexity as a hard decoder. It can fit well for 10–40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115271642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044985
Chia-Min Chen, C. Hung
A fast self-reacting (FSR) low-dropout (LDO) regulator with triple transient improved loops was implemented in 0.35μm CMOS technology. The proposed regulator for SoC application can achieve high stability for load current from zero to 100mA. The FSR loops can accelerate load transient responses while the regulator achieves the FOM of only 0.00675 (ps) without an output capacitor. The experimental results show the load regulation of 75.2 μV/mA and line regulation of 1.046 mV/V. The whole LDO chip consumes a quiescent current of 27 μA with an ultra low dropout voltage of 142mV at the maximum output current of 100mA. The proposed FSR transient improved loops can effectively reduce the transient voltage undershoot and overshoot. While the load current switches between 0 and 100 mA with both rise and fall time of 1 μs, the result shows that the maximum undershoot is 25 mV and that the maximum overshoot is 5 mV. When the full load current is 100mA, the undershoot and the overshoot of the line transient response are 4 mV and 6.5 mV, respectively, for a 1 V step supply waveform with 5 μs transient time.
{"title":"A fast self-reacting capacitor-less low-dropout regulator","authors":"Chia-Min Chen, C. Hung","doi":"10.1109/ESSCIRC.2011.6044985","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044985","url":null,"abstract":"A fast self-reacting (FSR) low-dropout (LDO) regulator with triple transient improved loops was implemented in 0.35μm CMOS technology. The proposed regulator for SoC application can achieve high stability for load current from zero to 100mA. The FSR loops can accelerate load transient responses while the regulator achieves the FOM of only 0.00675 (ps) without an output capacitor. The experimental results show the load regulation of 75.2 μV/mA and line regulation of 1.046 mV/V. The whole LDO chip consumes a quiescent current of 27 μA with an ultra low dropout voltage of 142mV at the maximum output current of 100mA. The proposed FSR transient improved loops can effectively reduce the transient voltage undershoot and overshoot. While the load current switches between 0 and 100 mA with both rise and fall time of 1 μs, the result shows that the maximum undershoot is 25 mV and that the maximum overshoot is 5 mV. When the full load current is 100mA, the undershoot and the overshoot of the line transient response are 4 mV and 6.5 mV, respectively, for a 1 V step supply waveform with 5 μs transient time.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124427643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044948
J. Bergervoet, D. Leenaerts, G. D. Jong, E. V. D. Heijden, J. Lobeek, A. Simin
A silicon integrated LNA for WCDMA cellular infrastructure applications, e.g. base stations will be demonstrated. The LNA is designed for the 1.92–1.98GHz band and reaches a 0.7dB NF at 27°C and 1.1 at 65°C. The output IP3 is +40dBm at 27°C and +37dBm at 65°C while having input and output return loss better than 20dB. A bypass mode and variable attenuation is also provided to cope with large input signals. The two-die MMIC is packaged on a single laminate. The total solution consumes a maximum of 197mA from a 5V supply.
将演示用于WCDMA蜂窝基础设施应用(例如基站)的硅集成LNA。LNA设计用于1.92-1.98GHz频段，在27°C时达到0.7dB NF，在65°C时达到1.1 db NF。输出IP3在27°C时为+40dBm，在65°C时为+37dBm，输入输出回波损耗均优于20dB。旁路模式和可变衰减也提供，以应付大的输入信号。双模MMIC封装在单一层压板上。整个解决方案从5V电源中最大消耗197mA。
{"title":"A 1.95GHz sub-1dB NF, +40dBm OIP3 WCDMA LNA with variable attenuation in SiGe:C BiCMOS","authors":"J. Bergervoet, D. Leenaerts, G. D. Jong, E. V. D. Heijden, J. Lobeek, A. Simin","doi":"10.1109/ESSCIRC.2011.6044948","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044948","url":null,"abstract":"A silicon integrated LNA for WCDMA cellular infrastructure applications, e.g. base stations will be demonstrated. The LNA is designed for the 1.92–1.98GHz band and reaches a 0.7dB NF at 27°C and 1.1 at 65°C. The output IP3 is +40dBm at 27°C and +37dBm at 65°C while having input and output return loss better than 20dB. A bypass mode and variable attenuation is also provided to cope with large input signals. The two-die MMIC is packaged on a single laminate. The total solution consumes a maximum of 197mA from a 5V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"56 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120934260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044960
Kameswaran Vengattaramane, J. Borremans, M. Steyaert, J. Craninckx
This paper presents a standard-cell based All-Digital Time-to-Digital Converter with reconfigurable resolution reaching sub-gate delay. The architecture based on spatial oversampling is implemented with an automated digital design flow. It features a robust online background calibration scheme for gain tracking. A 90 nm prototype chip achieves [39–14] ps effective resolution consuming [1–8] mA, in an area of only 0.26 mm2
{"title":"A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration","authors":"Kameswaran Vengattaramane, J. Borremans, M. Steyaert, J. Craninckx","doi":"10.1109/ESSCIRC.2011.6044960","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044960","url":null,"abstract":"This paper presents a standard-cell based All-Digital Time-to-Digital Converter with reconfigurable resolution reaching sub-gate delay. The architecture based on spatial oversampling is implemented with an automated digital design flow. It features a robust online background calibration scheme for gain tracking. A 90 nm prototype chip achieves [39–14] ps effective resolution consuming [1–8] mA, in an area of only 0.26 mm2","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127075128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044917
Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee
This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm2 in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs.
{"title":"A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence","authors":"Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ESSCIRC.2011.6044917","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044917","url":null,"abstract":"This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm2 in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127161869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044995
D. Raiteri, F. Torricelli, E. Cantatore, A. Roermund
This paper presents a transconductor designed using a physical model of double-gate p-type organic thin film transistors (OTFTs). A control voltage can be used to vary the output resistance and the transconductance over one order of magnitude. The voltage gain does not depend on process parameters and therefore is insensitive to shelf and operational degradation. This circuit can be used as a tunable resistor, in voltage amplifiers or in GmC filters.
{"title":"A tunable transconductor for analog amplification and filtering based on double-gate organic TFTs","authors":"D. Raiteri, F. Torricelli, E. Cantatore, A. Roermund","doi":"10.1109/ESSCIRC.2011.6044995","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044995","url":null,"abstract":"This paper presents a transconductor designed using a physical model of double-gate p-type organic thin film transistors (OTFTs). A control voltage can be used to vary the output resistance and the transconductance over one order of magnitude. The voltage gain does not depend on process parameters and therefore is insensitive to shelf and operational degradation. This circuit can be used as a tunable resistor, in voltage amplifiers or in GmC filters.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127285728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044962
Z. Tan, M. Pertijs, G. Meijer
This paper presents a period-modulator based capacitive sensor interface implemented using energy-efficient building blocks. The integrator in the modulator is based on a current-efficient telescopic OTA, whose limited output swing is accommodated using negative feedback loops. The use of a low-power comparator is enabled by eliminating errors associated with its propagation time using auto-calibration. The interface has been implemented in 0.35 μm standard CMOS technology. Experimental results show that for a capacitance range of 6.8 pF, the interface achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms, while consuming only 64 μA from a 3.3 V power supply. Compared to previous work with similar performance, this represents a significant improvement in energy efficiency.
{"title":"An energy-efficient 15-bit capacitive sensor interface","authors":"Z. Tan, M. Pertijs, G. Meijer","doi":"10.1109/ESSCIRC.2011.6044962","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044962","url":null,"abstract":"This paper presents a period-modulator based capacitive sensor interface implemented using energy-efficient building blocks. The integrator in the modulator is based on a current-efficient telescopic OTA, whose limited output swing is accommodated using negative feedback loops. The use of a low-power comparator is enabled by eliminating errors associated with its propagation time using auto-calibration. The interface has been implemented in 0.35 μm standard CMOS technology. Experimental results show that for a capacitance range of 6.8 pF, the interface achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms, while consuming only 64 μA from a 3.3 V power supply. Compared to previous work with similar performance, this represents a significant improvement in energy efficiency.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125901540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044994
H. Marien, M. Steyaert, E. Veenendaal, P. Heremans
In this work an organic dual DC-DC up-converter and an organic 2-stage operational amplifier are presented, both implemented in a thin-film organic electronics technology on foil. The converter has a conversion ratio of 2.5 and only consumes 1 μA from a 15 V power supply voltage. The converter is designed for biasing gates and backgates of transistors in a p-type only technology and enables to bias both input and output nodes of a differential amplifier to the same DC voltage. This in turn enables to directly connect consecutive differential amplifier stages together. The latter is demonstrated through the 2-stage operational amplifier that has a measured gain of 20 dB and a gain-bandwidth product of 2 kHz. This opamp consumes 15 μA from a 15 V power supply.
{"title":"DC-DC converter assisted two-stage amplifier in organic thin-film transistor technology on foil","authors":"H. Marien, M. Steyaert, E. Veenendaal, P. Heremans","doi":"10.1109/ESSCIRC.2011.6044994","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044994","url":null,"abstract":"In this work an organic dual DC-DC up-converter and an organic 2-stage operational amplifier are presented, both implemented in a thin-film organic electronics technology on foil. The converter has a conversion ratio of 2.5 and only consumes 1 μA from a 15 V power supply voltage. The converter is designed for biasing gates and backgates of transistors in a p-type only technology and enables to bias both input and output nodes of a differential amplifier to the same DC voltage. This in turn enables to directly connect consecutive differential amplifier stages together. The latter is demonstrated through the 2-stage operational amplifier that has a measured gain of 20 dB and a gain-bandwidth product of 2 kHz. This opamp consumes 15 μA from a 15 V power supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125395765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6045011
R. Pilawa-Podgurski, D. Perreault
In this paper, we introduce a merged two-stage dc-dc power converter for low-voltage power delivery. By separating the transformation and regulation function of a dc-dc power converter into two stages, both large voltage transformation and high control bandwidth can be achieved. We show how the switched-capacitor stage can operate under soft charging conditions by suitable control and integration (merging) of the two stages. This mode of operation enables improved efficiency and/or power density in the switched-capacitor stage. A 5-to-1 V, 0.8 W integrated dc-dc converter has been developed in 180 nm CMOS. The converter achieves a peak efficiency of 81%, with a regulation stage switching frequency of 10 MHz.
本文介绍了一种用于低压输电的合并两级dc-dc电源变换器。将dc-dc功率变换器的变换和调节功能分为两级，既可以实现大电压变换，又可以实现高控制带宽。我们展示了如何通过适当的控制和两个阶段的集成(合并)来实现开关电容器阶段在软充电条件下的工作。这种操作模式可以提高开关电容器阶段的效率和/或功率密度。研制了一种5 to 1 V、0.8 W的集成dc-dc变换器。该变换器的峰值效率为81%，调节级开关频率为10 MHz。
{"title":"Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOS","authors":"R. Pilawa-Podgurski, D. Perreault","doi":"10.1109/ESSCIRC.2011.6045011","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045011","url":null,"abstract":"In this paper, we introduce a merged two-stage dc-dc power converter for low-voltage power delivery. By separating the transformation and regulation function of a dc-dc power converter into two stages, both large voltage transformation and high control bandwidth can be achieved. We show how the switched-capacitor stage can operate under soft charging conditions by suitable control and integration (merging) of the two stages. This mode of operation enables improved efficiency and/or power density in the switched-capacitor stage. A 5-to-1 V, 0.8 W integrated dc-dc converter has been developed in 180 nm CMOS. The converter achieves a peak efficiency of 81%, with a regulation stage switching frequency of 10 MHz.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128961464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 90-nm CMOS, 6-GHz spread-spectrum clock generator (SSCG) showing low jitter and the feasible electromagnetic interference (EMI) reduction is presented. Forsaking the commonly used ΔΣ technique for the average fractional-N ratios by the dithering, the proposed SSCG uses a phase-rotating technique to realize truly fractional division ratios, and creates the spread-spread clocking (SSC) by modulating the fractional-N ratios. The phase-rotating technique effectively calibrates instantaneous timing error and shows ignorable quantization error. Operating at a 6-GHz clock rate, the measured RMS jitter with and without a 0.5% (5000-ppm) down-spreading spectrum are 0.77 ps and 0.71 ps, respectively, showing a significant improvement in the suppressed sub-1ps RMS jitter and the mere increase in RMS jitter of 0.06 ps while implementing SSC. As the serial AT attachment (SATA) standard suggesting the 100 kHz-RBW for the instruments, the measured power attenuation of EMI is 16.12 dB under a 5000-ppm frequency deviation. The chip core area is less than 0.55 × 0.45 mm2, and the core power consumption is 27.7 mW at a 1.0-V supply.
{"title":"A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation","authors":"Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, C. Fan, Chi-Yang Chang","doi":"10.1109/ESSCIRC.2011.6045003","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6045003","url":null,"abstract":"A 90-nm CMOS, 6-GHz spread-spectrum clock generator (SSCG) showing low jitter and the feasible electromagnetic interference (EMI) reduction is presented. Forsaking the commonly used ΔΣ technique for the average fractional-N ratios by the dithering, the proposed SSCG uses a phase-rotating technique to realize truly fractional division ratios, and creates the spread-spread clocking (SSC) by modulating the fractional-N ratios. The phase-rotating technique effectively calibrates instantaneous timing error and shows ignorable quantization error. Operating at a 6-GHz clock rate, the measured RMS jitter with and without a 0.5% (5000-ppm) down-spreading spectrum are 0.77 ps and 0.71 ps, respectively, showing a significant improvement in the suppressed sub-1ps RMS jitter and the mere increase in RMS jitter of 0.06 ps while implementing SSC. As the serial AT attachment (SATA) standard suggesting the 100 kHz-RBW for the instruments, the measured power attenuation of EMI is 16.12 dB under a 5000-ppm frequency deviation. The chip core area is less than 0.55 × 0.45 mm2, and the core power consumption is 27.7 mW at a 1.0-V supply.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130352638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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