An improved low power high speed Full Adder design with 28nm for extended region of operation

Abstract

This work holds the objective of investigating the performance of conventional Full Adders (FA) at 28nm regime and then proposes a Transmission Gate (TG) based improved FA circuit of reduced Power Delay Product (PDP). In this design the XOR/XNOR nodes have been optimized to operate at submicron level with lower delay. The work provides full voltage swing even at lower operating voltage by avoiding the threshold loss problem. The low leakage feature of TG technology allows it to deliver high energy efficiency. The modified circuit achieves up to 59.14% and 59.36% improvements in worst case delay and PDP respectively as compared to the conventional TG based FA cells for low power mode of operation. Particularly at lower voltage range and higher speed, the performance is considerably fair. Simulations show that the modified FA circuit is efficient in terms of delay as well as extended region of operation. All simulations are performed with Cadence Virtuoso tool and Eldo simulator for 28nm FDSOI technology.