Methods for synthesizing testable sequential circuits

Abstract

We present three approaches to designing testable sequential machines. (Testability, in the present context, refers to the ability to generate tests. Testable synthesis guarantees high fault coverage by using an automatic test generator.) In the first approach, we develop a partial scan method in which scan flip-flops are selected to break up the cyclic structure of the sequential circuit. In the second approach, we present a novel state assignment method that results in reduced feedback or pipeline-like structure. The third approach, also applicable to finite state machines, embeds a suitably designed test machine in the given specification before synthesis.