Pub Date : 2018-12-31DOI: 10.7591/9781501714795-003
G. Swart
CFR Code of Federal Regulations DOE U.S. Department of Energy (also called the Department) EIS environmental impact statement EPA U.S. Environmental Protection Agency FR Federal Register LCF latent cancer fatality MTHM metric tons of heavy metal NEPA National Environmental Policy Act, as amended NRC U.S. Nuclear Regulatory Commission NWPA Nuclear Waste Policy Act, as amended PM10 particulate matter with an aerodynamic diameter of 10 micrometers or less PM2.5 particulate matter with an aerodynamic diameter of 2.5 micrometers or less REMI Regional Economic Models, Inc. RMEI reasonably maximally exposed individual Stat. United States Statutes TSPA Total System Performance Assessment U.S.C. United States Code
{"title":"Acronyms and abbreviations","authors":"G. Swart","doi":"10.7591/9781501714795-003","DOIUrl":"https://doi.org/10.7591/9781501714795-003","url":null,"abstract":"CFR Code of Federal Regulations DOE U.S. Department of Energy (also called the Department) EIS environmental impact statement EPA U.S. Environmental Protection Agency FR Federal Register LCF latent cancer fatality MTHM metric tons of heavy metal NEPA National Environmental Policy Act, as amended NRC U.S. Nuclear Regulatory Commission NWPA Nuclear Waste Policy Act, as amended PM10 particulate matter with an aerodynamic diameter of 10 micrometers or less PM2.5 particulate matter with an aerodynamic diameter of 2.5 micrometers or less REMI Regional Economic Models, Inc. RMEI reasonably maximally exposed individual Stat. United States Statutes TSPA Total System Performance Assessment U.S.C. United States Code","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121816871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-03-04DOI: 10.1002/J.1538-7305.1993.TB00531.X
M. Berg, Neil E. Gallensky, G. D. Hamilton, Won U. Huh, J. L. Knight, John J. Sangermano
To serve the global marketplace effectively, AT&T's private branch exchange (PBX) hardware must be adaptable to a wide range of technical and regulatory environments quickly and at minimal cost. To control the potential expense of resolving hardware problems in remote areas, a high level of system reliability must be ensured. This paper presents the reasons for providing hardware adaptability and outlines seven dimensions of the global design problem. It also explores issues confronted in creating the proper degree of hardware flexibility, the design technologies used to address these issues, and AT&T's current, overall approach to global hardware engineering.
{"title":"World-class hardware and transmission design","authors":"M. Berg, Neil E. Gallensky, G. D. Hamilton, Won U. Huh, J. L. Knight, John J. Sangermano","doi":"10.1002/J.1538-7305.1993.TB00531.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1993.TB00531.X","url":null,"abstract":"To serve the global marketplace effectively, AT&T's private branch exchange (PBX) hardware must be adaptable to a wide range of technical and regulatory environments quickly and at minimal cost. To control the potential expense of resolving hardware problems in remote areas, a high level of system reliability must be ensured. This paper presents the reasons for providing hardware adaptability and outlines seven dimensions of the global design problem. It also explores issues confronted in creating the proper degree of hardware flexibility, the design technologies used to address these issues, and AT&T's current, overall approach to global hardware engineering.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119331891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-01DOI: 10.1002/J.1538-7305.1991.TB00354.X
M. J. Morgan, Michael J. Cosky, T. Gruenenfelder, T. Holmes, G. A. Raack
An intelligent network lets a switch query a network node for help in completing a call. Such a node, for example, can translate an 800 number into a true network address. The network service provider often creates the logic in an intelligent network, but frequently that logic is written by sophisticated subscribers (business customers). Since subscribers can create their own service logic, the service creation system must ensure that such customized logic will not cause the network node to fail or in any way affect the service of other subscribers. Service creation technologies are the tools and technical infrastructure designed specifically to help create and update services. AT&T has created software tools to support application-oriented languages. Its service creation technologies are evolving to meet service provider and service subscriber demands for more control over the services they provide and use.
{"title":"Service creation technologies for the intelligent network","authors":"M. J. Morgan, Michael J. Cosky, T. Gruenenfelder, T. Holmes, G. A. Raack","doi":"10.1002/J.1538-7305.1991.TB00354.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1991.TB00354.X","url":null,"abstract":"An intelligent network lets a switch query a network node for help in completing a call. Such a node, for example, can translate an 800 number into a true network address. The network service provider often creates the logic in an intelligent network, but frequently that logic is written by sophisticated subscribers (business customers). Since subscribers can create their own service logic, the service creation system must ensure that such customized logic will not cause the network node to fail or in any way affect the service of other subscribers. Service creation technologies are the tools and technical infrastructure designed specifically to help create and update services. AT&T has created software tools to support application-oriented languages. Its service creation technologies are evolving to meet service provider and service subscriber demands for more control over the services they provide and use.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118683600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-01DOI: 10.1002/J.1538-7305.1991.TB00353.X
Alexandra M. Workman, Murthy V. Kolipakam, J. B. Sharpless, V. Stoss, Hans van der Veer
On November 7, 1988 the Digital Derived Services Network (DDSN) in the United Kingdom began providing switch-based Freephone service to British Telecom's (BT) customers. On January 29, 1990, advanced Freephone services were first offered to BT's customers. With the deployment of DDSN in the U. K., AT&T became the first equipment vendor to implement an intelligent network (IN) outside its base country. In addition to DDSN, in 1990 AT&T installed an IN in Spain, and is currently installing another in Italy. AT&T's experience with its international customers has encouraged developing a platform to address international IN needs. This paper discusses the critical components of this platform, and describes the IN architecture and operations systems of the British, Spanish, and Italian networks. It also presents a strategy for evolving these networks in a world of new and evolving services and standards.
{"title":"International applications of AT&T's intelligent network platforms","authors":"Alexandra M. Workman, Murthy V. Kolipakam, J. B. Sharpless, V. Stoss, Hans van der Veer","doi":"10.1002/J.1538-7305.1991.TB00353.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1991.TB00353.X","url":null,"abstract":"On November 7, 1988 the Digital Derived Services Network (DDSN) in the United Kingdom began providing switch-based Freephone service to British Telecom's (BT) customers. On January 29, 1990, advanced Freephone services were first offered to BT's customers. With the deployment of DDSN in the U. K., AT&T became the first equipment vendor to implement an intelligent network (IN) outside its base country. In addition to DDSN, in 1990 AT&T installed an IN in Spain, and is currently installing another in Italy. AT&T's experience with its international customers has encouraged developing a platform to address international IN needs. This paper discusses the critical components of this platform, and describes the IN architecture and operations systems of the British, Spanish, and Italian networks. It also presents a strategy for evolving these networks in a world of new and evolving services and standards.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119854036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-01-02DOI: 10.1002/J.1538-7305.1991.TB00494.X
M. S. Toth
With the increased sophistication of analog-circuit simulation tools comes a heavier reliance on the interfaces to these tools. Today, designers can control simulation tools through programs — a technique referred to as procedural simulation — and derive performance measures (e.g., common-mode rejection ratio, bandwidth, etc.) easily from more-basic circuit-simulation variables (i.e., voltages and currents). This technique has proved to be a valuable feature of AT&T's analog-circuit simulator, ADVICE. To enable designers to exploit procedural simulation more fully, a program called makca1 was created. Makca1 writes a procedural-simulation program that a designer can use to control ADVICE. Makca1 includes the capability to select and present performance measures in a variety of graphic and textual formats. Because makca1 streamlines the programming process, designers can concentrate more fully on designing, which reduces the product's time to market.
{"title":"Makcal: An application generator for advice","authors":"M. S. Toth","doi":"10.1002/J.1538-7305.1991.TB00494.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1991.TB00494.X","url":null,"abstract":"With the increased sophistication of analog-circuit simulation tools comes a heavier reliance on the interfaces to these tools. Today, designers can control simulation tools through programs — a technique referred to as procedural simulation — and derive performance measures (e.g., common-mode rejection ratio, bandwidth, etc.) easily from more-basic circuit-simulation variables (i.e., voltages and currents). This technique has proved to be a valuable feature of AT&T's analog-circuit simulator, ADVICE. To enable designers to exploit procedural simulation more fully, a program called makca1 was created. Makca1 writes a procedural-simulation program that a designer can use to control ADVICE. Makca1 includes the capability to select and present performance measures in a variety of graphic and textual formats. Because makca1 streamlines the programming process, designers can concentrate more fully on designing, which reduces the product's time to market.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123347942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-01-02DOI: 10.1002/J.1538-7305.1991.TB00498.X
K. Cheng, V. Agrawal
We present three approaches to designing testable sequential machines. (Testability, in the present context, refers to the ability to generate tests. Testable synthesis guarantees high fault coverage by using an automatic test generator.) In the first approach, we develop a partial scan method in which scan flip-flops are selected to break up the cyclic structure of the sequential circuit. In the second approach, we present a novel state assignment method that results in reduced feedback or pipeline-like structure. The third approach, also applicable to finite state machines, embeds a suitably designed test machine in the given specification before synthesis.
{"title":"Methods for synthesizing testable sequential circuits","authors":"K. Cheng, V. Agrawal","doi":"10.1002/J.1538-7305.1991.TB00498.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1991.TB00498.X","url":null,"abstract":"We present three approaches to designing testable sequential machines. (Testability, in the present context, refers to the ability to generate tests. Testable synthesis guarantees high fault coverage by using an automatic test generator.) In the first approach, we develop a partial scan method in which scan flip-flops are selected to break up the cyclic structure of the sequential circuit. In the second approach, we present a novel state assignment method that results in reduced feedback or pipeline-like structure. The third approach, also applicable to finite state machines, embeds a suitably designed test machine in the given specification before synthesis.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117254502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-01-02DOI: 10.1002/J.1538-7305.1991.TB00495.X
P. Agrawal, Chong Hoc Hao, M. Remillard
Design verification of large VLSI (very-large-scale integration) circuits accounts for a sizable part of design time. Simulators verify the design at various levels of abstraction. A fast and accurate simulator enables the designer to introduce a higher quality product into the marketplace early. This paper describes a logic simulator implemented using the MARS (Microprogrammable Accelerator for Rapid Simulations) multicomputer. The logic simulator, AGSIM (Accelerated Good Circuit Simulator), has been integrated into the production CAD (computer-aided design) system at AT&T Bell Laboratories. To date, more than 200 application-specific integrated circuits (ASICs) of varying complexity have been simulated with MARS. This paper presents the relevant features of the MARS architecture, and the details of the logic simulator. We present the results on 10 VLSI ASIC simulations to show its increased performance over the existing software simulator, GSIM (Good Circuit Simulator), while maintaining the same accuracy. The MARS project started with accelerated logic simulation as the primary application. However, the programmable nature of the accelerator has made several other applications possible.
大型VLSI(超大规模集成电路)电路的设计验证占设计时间的相当一部分。模拟器在不同的抽象层次上验证设计。一个快速和准确的模拟器使设计人员能够尽早向市场推出更高质量的产品。本文介绍了一种利用MARS (Microprogrammable Accelerator for Rapid Simulations)多计算机实现的逻辑模拟器。逻辑模拟器AGSIM(加速良好电路模拟器)已经集成到AT&T贝尔实验室的生产CAD(计算机辅助设计)系统中。迄今为止，已有超过200种不同复杂性的专用集成电路(asic)被MARS模拟。本文介绍了MARS体系结构的相关特点，以及逻辑模拟器的详细设计。我们展示了10个VLSI ASIC模拟的结果，以显示其比现有软件模拟器GSIM (Good Circuit simulator)的性能有所提高，同时保持相同的精度。MARS项目以加速逻辑仿真作为主要应用开始。然而，加速器的可编程特性使其他几个应用成为可能。
{"title":"Logic simulation on the MARS multicomputer","authors":"P. Agrawal, Chong Hoc Hao, M. Remillard","doi":"10.1002/J.1538-7305.1991.TB00495.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1991.TB00495.X","url":null,"abstract":"Design verification of large VLSI (very-large-scale integration) circuits accounts for a sizable part of design time. Simulators verify the design at various levels of abstraction. A fast and accurate simulator enables the designer to introduce a higher quality product into the marketplace early. This paper describes a logic simulator implemented using the MARS (Microprogrammable Accelerator for Rapid Simulations) multicomputer. The logic simulator, AGSIM (Accelerated Good Circuit Simulator), has been integrated into the production CAD (computer-aided design) system at AT&T Bell Laboratories. To date, more than 200 application-specific integrated circuits (ASICs) of varying complexity have been simulated with MARS. This paper presents the relevant features of the MARS architecture, and the details of the logic simulator. We present the results on 10 VLSI ASIC simulations to show its increased performance over the existing software simulator, GSIM (Good Circuit Simulator), while maintaining the same accuracy. The MARS project started with accelerated logic simulation as the primary application. However, the programmable nature of the accelerator has made several other applications possible.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117275648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-01-02DOI: 10.1002/J.1538-7305.1991.TB00497.X
J. Coplien
This system-development environment is a companion to SysCAD that permits users to specify, prototype, simulate, develop, and document a complex digital system. ISHMAEL can manage the simultaneous evolution of a system's software and hardware. ISHMAEL users can develop faithful models of system performance that simulate the interaction of hardware and software at any level of detail. They can iterate hardware and software designs during a simulation, which permits realistic evaluation of design tradeoffs and implementation alternatives early in a system's life cycle and, thus, reduces system costs. ISHMAEL's integrated, graphical interface provides several views of the application being developed: a high-level or a detailed (i.e., schematic) hardware view, and the application-user's view. The system was used for prototyping, specification, evaluation, and implementation of a highly distributed, telecommunications system.
{"title":"ISHMAEL: An integrated software/hardware maintenance and evolution environment","authors":"J. Coplien","doi":"10.1002/J.1538-7305.1991.TB00497.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1991.TB00497.X","url":null,"abstract":"This system-development environment is a companion to SysCAD that permits users to specify, prototype, simulate, develop, and document a complex digital system. ISHMAEL can manage the simultaneous evolution of a system's software and hardware. ISHMAEL users can develop faithful models of system performance that simulate the interaction of hardware and software at any level of detail. They can iterate hardware and software designs during a simulation, which permits realistic evaluation of design tradeoffs and implementation alternatives early in a system's life cycle and, thus, reduces system costs. ISHMAEL's integrated, graphical interface provides several views of the application being developed: a high-level or a detailed (i.e., schematic) hardware view, and the application-user's view. The system was used for prototyping, specification, evaluation, and implementation of a highly distributed, telecommunications system.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114552844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-01-02DOI: 10.1002/J.1538-7305.1991.TB00493.X
J. Foster
Computer-aided engineering/computer-aided design (CAE/CAD) tools have in the past and will in the future play an important role in the design of AT&T hardware products. Currently, CAE/CAD tools are being used to decrease overall product time-to-market and increase product quality, specifically in the areas of design verification and synthesis. This issue of the AT&T Technical Journal contains papers based on the topics presented at the AT&T CAE/CAD symposium, held in Murray Hill, New Jersey, on October 18, 1989. This paper discusses CAE/CAD in general, as well as its past and future roles in AT&T. It also introduces each paper in this issue and describes its relationship to advances in the field of CAE/CAD technology.
{"title":"CAE/CAD at AT&T: An introduction","authors":"J. Foster","doi":"10.1002/J.1538-7305.1991.TB00493.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1991.TB00493.X","url":null,"abstract":"Computer-aided engineering/computer-aided design (CAE/CAD) tools have in the past and will in the future play an important role in the design of AT&T hardware products. Currently, CAE/CAD tools are being used to decrease overall product time-to-market and increase product quality, specifically in the areas of design verification and synthesis. This issue of the AT&T Technical Journal contains papers based on the topics presented at the AT&T CAE/CAD symposium, held in Murray Hill, New Jersey, on October 18, 1989. This paper discusses CAE/CAD in general, as well as its past and future roles in AT&T. It also introduces each paper in this issue and describes its relationship to advances in the field of CAE/CAD technology.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122061142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-01-02DOI: 10.1002/J.1538-7305.1991.TB00500.X
J. Schmidt, T. Kowalski, David S. Smull
We have developed an incremental computer-aided design library that provides run-time facilities to link, unlink, execute, and list functions. At the heart of the library is an incremental loader that helps designers and users customize their basic tool for their design environment. In this paper, we discuss how four computer-aided design tools have benefited from using the library for simulating C-language models, modifying and enhancing graphical user interfaces, extending command languages, and rapidly testing new functionality. Using SCHEMA and MIDAS as case studies, we also describe how the library improves quality and reduces time to market.
{"title":"An incremental environment for computer-aided design tools","authors":"J. Schmidt, T. Kowalski, David S. Smull","doi":"10.1002/J.1538-7305.1991.TB00500.X","DOIUrl":"https://doi.org/10.1002/J.1538-7305.1991.TB00500.X","url":null,"abstract":"We have developed an incremental computer-aided design library that provides run-time facilities to link, unlink, execute, and list functions. At the heart of the library is an incremental loader that helps designers and users customize their basic tool for their design environment. In this paper, we discuss how four computer-aided design tools have benefited from using the library for simulating C-language models, modifying and enhancing graphical user interfaces, extending command languages, and rapidly testing new functionality. Using SCHEMA and MIDAS as case studies, we also describe how the library improves quality and reduces time to market.","PeriodicalId":170077,"journal":{"name":"AT&T Technical Journal","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128652085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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