A multi-threading architecture for multilevel secure transaction processing

Haruna R. Isa, W. Shockley, C. Irvine
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引用次数: 4

Abstract

A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design exploits hardware security features of the Intel 80/spl times/86 processor family. Intel's CPU architecture provides hardware with two distinct descriptor tables. We use one of these in the usual way for process isolation. For each process, the descriptor table holds the descriptors of "system-low" segments, such as code segments, used by every thread in a process. We use the second table to hold descriptors for segments known to individual threads within the process. This allocation, together with an appropriately designed scheduling policy, permits us to avoid the full cost of process creation when only switching between threads of different security classes in the same process. Where large numbers of transactions are encountered on transaction queues, this approach has benefits over traditional multilevel systems.
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用于多级安全事务处理的多线程体系结构
提出了一种支持多层安全环境中多线程、队列驱动的事务处理应用程序的TCB和安全内核体系结构。我们的设计利用了Intel 80/spl times/86处理器家族的硬件安全特性。Intel的CPU架构为硬件提供了两个不同的描述符表。我们以通常的方式使用其中一个来进行进程隔离。对于每个进程,描述符表保存“system-low”段的描述符,例如进程中的每个线程使用的代码段。我们使用第二个表来保存进程中各个线程已知的段的描述符。这种分配,加上适当设计的调度策略,允许我们在同一进程中仅在不同安全类的线程之间切换时避免进程创建的全部成本。当事务队列上遇到大量事务时,这种方法比传统的多层系统更有优势。
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