{"title":"A 2000 Gate Bipolar Uncommitted Logic Array","authors":"S. Colaco, H. Hulmes","doi":"10.1109/ESSCIRC.1980.5468739","DOIUrl":null,"url":null,"abstract":"A 2000 gate high speed Bipolar Uncommitted Logic Array using 3 micrometer minimum feature sizes has been described, The chip comprises 1980 CML gates and 64 I/O cells. Typical gate delay is 6 nanoseconds. Power Delay time produced is 0.5 pJ. A single 5 volt supply powers the chip which is fully T.T.L. compatible.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 80: 6th European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1980.5468739","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 2000 gate high speed Bipolar Uncommitted Logic Array using 3 micrometer minimum feature sizes has been described, The chip comprises 1980 CML gates and 64 I/O cells. Typical gate delay is 6 nanoseconds. Power Delay time produced is 0.5 pJ. A single 5 volt supply powers the chip which is fully T.T.L. compatible.
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