Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468720
P. Amblard, G. Saucier
The design methodology for complex integrated controllers presented here has two main features : it is a multilevel safe approach, it separates clearly the design choices and automatic design procedures, being computer aided for this last point.
{"title":"Design Methodology of Controllers","authors":"P. Amblard, G. Saucier","doi":"10.1109/ESSCIRC.1980.5468720","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468720","url":null,"abstract":"The design methodology for complex integrated controllers presented here has two main features : it is a multilevel safe approach, it separates clearly the design choices and automatic design procedures, being computer aided for this last point.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125240095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468725
J. Picquendar
Summary form only given. Talking once again of P.C.M transmission, we must mention the multiples of order higher than 32, whose signals are obtained by successive concatenation of P.C.M. (base) signals. The analog multiplex transmission required the development of high performance components, such as transistors used in multiplex analog links at 60 MHz (10.800 channels), having very low noise figure and transition frequency higher than 3 GHz.
{"title":"Special transmission components","authors":"J. Picquendar","doi":"10.1109/ESSCIRC.1980.5468725","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468725","url":null,"abstract":"Summary form only given. Talking once again of P.C.M transmission, we must mention the multiples of order higher than 32, whose signals are obtained by successive concatenation of P.C.M. (base) signals. The analog multiplex transmission required the development of high performance components, such as transistors used in multiplex analog links at 60 MHz (10.800 channels), having very low noise figure and transition frequency higher than 3 GHz.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117031986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468766
D. Omet
A double 576 bits random access memory organized as 2×32 words by 18 bits has been designed, completely tested, and qualified from a functionality and reliability point of view. The two major advantages of this memory are a good speedpower trade off for this particular type of organization and its ability to work with two independant 18 bits I/O busses.
{"title":"A 10ns Bipolar Memory, Working with 18 I/O Bus","authors":"D. Omet","doi":"10.1109/ESSCIRC.1980.5468766","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468766","url":null,"abstract":"A double 576 bits random access memory organized as 2×32 words by 18 bits has been designed, completely tested, and qualified from a functionality and reliability point of view. The two major advantages of this memory are a good speedpower trade off for this particular type of organization and its ability to work with two independant 18 bits I/O busses.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129631909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468774
Mohamed H. Elsaid, Ali M. Hashed
A new poly I2L structure with switching speed three times higher than that of the conventional I2L structure is presented. The packing density is also improved by a factor of two using this new structure.
提出了一种开关速度比传统I2L结构快3倍的新型多晶硅结构。采用这种新结构，填料密度也提高了两倍。
{"title":"High Speed High Density Poly I2L","authors":"Mohamed H. Elsaid, Ali M. Hashed","doi":"10.1109/ESSCIRC.1980.5468774","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468774","url":null,"abstract":"A new poly I2L structure with switching speed three times higher than that of the conventional I2L structure is presented. The packing density is also improved by a factor of two using this new structure.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"127 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114017750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468729
J. Picquendar
Summary form only given. This ensemble replaces the rotary, crossbar type, spatial switching systems. In earlier days, these formed the bigger part of an exchange. With temporal switching, the number of chips has been considerably reduced. Considering that the natural support of speech signal is the "P.CM. time slot", the "switch" is a mixer of coded pulse trains which works as follows : it does an "application" (in the mathematical sense of the word) of the time intervals of 8 entering pulses (coded by P.CM.) to the time intervals of 8 outgoing pulses (coded by P.CM.). This appli cation follows a law that is already stored in the memory and which is modified only at the time of establishment or at the end of a telephone call. This represents an L.S.I, circuit using more than 30.000 transistors and working as a switch of 8 x 30 x 64 = 15 Mbits / second.
只提供摘要形式。这一组合取代了旋转式、横杆式、空间开关系统。在早期，这些构成了交易所的大部分。随着时间开关，芯片的数量已经大大减少。考虑到语音信号的自然支持是“pcm”。，“开关”是编码脉冲序列的混频器，其工作原理如下:它将8个输入脉冲(由P.CM编码)的时间间隔“应用”(在这个词的数学意义上)到8个输出脉冲(由P.CM编码)的时间间隔。此应用程序遵循已经存储在内存中的规律，并且仅在建立时或在电话呼叫结束时修改该规律。这代表了一个L.S.I电路，使用超过30,000个晶体管，作为8 x 30 x 64 = 15mbits / s的开关工作。
{"title":"The heart of the chaine (or connection network)","authors":"J. Picquendar","doi":"10.1109/ESSCIRC.1980.5468729","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468729","url":null,"abstract":"Summary form only given. This ensemble replaces the rotary, crossbar type, spatial switching systems. In earlier days, these formed the bigger part of an exchange. With temporal switching, the number of chips has been considerably reduced. Considering that the natural support of speech signal is the \"P.CM. time slot\", the \"switch\" is a mixer of coded pulse trains which works as follows : it does an \"application\" (in the mathematical sense of the word) of the time intervals of 8 entering pulses (coded by P.CM.) to the time intervals of 8 outgoing pulses (coded by P.CM.). This appli cation follows a law that is already stored in the memory and which is modified only at the time of establishment or at the end of a telephone call. This represents an L.S.I, circuit using more than 30.000 transistors and working as a switch of 8 x 30 x 64 = 15 Mbits / second.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127971912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468808
H. Betzl, H. Klar, M. Mauthe, W. Ulbrich
CCD resonators are very useful to build extremely sharp integrated filters. The basic resonator consisting of one closed CCD loop as well as an extension - the double resonator - are described.
{"title":"Passive Recursive CCD Resonators","authors":"H. Betzl, H. Klar, M. Mauthe, W. Ulbrich","doi":"10.1109/ESSCIRC.1980.5468808","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468808","url":null,"abstract":"CCD resonators are very useful to build extremely sharp integrated filters. The basic resonator consisting of one closed CCD loop as well as an extension - the double resonator - are described.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"429 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134089685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468778
F. Bertotti, P. Erratico, B. Murari
In this paper we present a review of the actual realizations and future trends for the power IC technologies. Two different processes for high voltage and high current are discussed and compared. Particular attention is devoted to surface stability phenomena and their implications on reliability. The actual panorama for medium and high power packages is discussed. Starting from the phisical limit of the maximum power that can "be dissipated in practical application conditions, we analyse the maximum power available at the out put for three classes of operations: DC, AC audio, and class D switching amplifiers. For the first two applications the actual limits appear to be set mainly by the extermal context (power supply regulation, thermal heatsink capability) instead of electrical performance of the silicon chip itself. So the actual implementations that provide 30 W continuous power and a voltage-current product in excess of 200 W, appear as a maximum. Class D limits appear to be mainly connected to the intrinsic characteristics of power devices, like sustaining-saturation voltage ratio, commutation speed and 2nd breakdown ruggedness. Actual implementations in 44 V technology reach 80 W for bipolar loads, so 150 W are possible when considering unipolar loads. But the new developments in power technologies indicate the way how to increase them.
{"title":"Future and Limits of Power I.C.","authors":"F. Bertotti, P. Erratico, B. Murari","doi":"10.1109/ESSCIRC.1980.5468778","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468778","url":null,"abstract":"In this paper we present a review of the actual realizations and future trends for the power IC technologies. Two different processes for high voltage and high current are discussed and compared. Particular attention is devoted to surface stability phenomena and their implications on reliability. The actual panorama for medium and high power packages is discussed. Starting from the phisical limit of the maximum power that can \"be dissipated in practical application conditions, we analyse the maximum power available at the out put for three classes of operations: DC, AC audio, and class D switching amplifiers. For the first two applications the actual limits appear to be set mainly by the extermal context (power supply regulation, thermal heatsink capability) instead of electrical performance of the silicon chip itself. So the actual implementations that provide 30 W continuous power and a voltage-current product in excess of 200 W, appear as a maximum. Class D limits appear to be mainly connected to the intrinsic characteristics of power devices, like sustaining-saturation voltage ratio, commutation speed and 2nd breakdown ruggedness. Actual implementations in 44 V technology reach 80 W for bipolar loads, so 150 W are possible when considering unipolar loads. But the new developments in power technologies indicate the way how to increase them.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116327830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468734
S. Hollock
The custom designed integrated circuit is the optimum method of producing an L.S.I, circuit of highest performance and maximum yield. The associated long design times and high development costs, however, generally restrict this approach to high volume or premium performance products. Several techniques have now been developed to speed the path from circuit specification to completed chip. These semi-custom techniques, which reduce design time and development cost at the expense of curtailed performance and increased device cost, make the custom I.C. an attractive proposition even for lower volume applications. They are also beginning to make possible significant reduction in system software costs.
{"title":"Semi-Custom I.C. A Way of Solving Non-Standard Lower Volume Applications","authors":"S. Hollock","doi":"10.1109/ESSCIRC.1980.5468734","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468734","url":null,"abstract":"The custom designed integrated circuit is the optimum method of producing an L.S.I, circuit of highest performance and maximum yield. The associated long design times and high development costs, however, generally restrict this approach to high volume or premium performance products. Several techniques have now been developed to speed the path from circuit specification to completed chip. These semi-custom techniques, which reduce design time and development cost at the expense of curtailed performance and increased device cost, make the custom I.C. an attractive proposition even for lower volume applications. They are also beginning to make possible significant reduction in system software costs.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"396 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122090990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468775
C. Tsironis, P. Harrop
Dual gate MESFET phase shifters have been realized in the frequency range of 3 GHz to 12 GHz. Linear phase variation of more than 100° and gain of 4 dB at 12 GHz and 50° with 11 dB gain at 6 GHz have been achieved.
{"title":"Phase Shifters with GaAs Dual Gate MESFETs","authors":"C. Tsironis, P. Harrop","doi":"10.1109/ESSCIRC.1980.5468775","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468775","url":null,"abstract":"Dual gate MESFET phase shifters have been realized in the frequency range of 3 GHz to 12 GHz. Linear phase variation of more than 100° and gain of 4 dB at 12 GHz and 50° with 11 dB gain at 6 GHz have been achieved.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129666845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1980-09-01DOI: 10.1109/ESSCIRC.1980.5468794
A. Suzim
The definition of a standard structure for Monolitic Microprocessor Data Processing Units enables us to build modular Data Processing Units (DPU) defined from a set of user parameters and a predesigned cell library.
{"title":"Modular Data Processing Units","authors":"A. Suzim","doi":"10.1109/ESSCIRC.1980.5468794","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1980.5468794","url":null,"abstract":"The definition of a standard structure for Monolitic Microprocessor Data Processing Units enables us to build modular Data Processing Units (DPU) defined from a set of user parameters and a predesigned cell library.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127400077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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