Method for Managing Electromigration in SOC'S When Designing for Both Reliability and Manufacturing

Abstract

Like design for manufacturing (DFM), design for reliability (DFR) of a chip identifies design features that are potentially vulnerable to various physical effects that can degrade circuit performance. The difference is that DFR attempts to model long-term effects, such as electromigration. Tools extract design information (resistances and current densities) and apply the data to simulation tools to estimate the degree of reliability. The weakness in this methodology is that these extraction technologies assume that the "as drawn" feature is a good representation of the "as manufactured" chip. DFM has shown that individual features on the "as manufactured" chip can vary dramatically from the intended layout in both critical dimension and thickness. The technologies developed to identify and characterize these DFM variations need to be incorporated into the DFR tools to accurately predict the long-term life of SoC nanometer designs.