All-Digital Phase Locked Loop with Single Reference Frequency Oscillator

D. Badarov, G. Mihov
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引用次数: 1

Abstract

All-digital Phase Locked Loop is designed in this article. A combinational frequency multiplier is developed and tested to achieve completely integrated system using only one low frequency reference oscillator. Adaptive proportional-integral regulation is used to ensure high stability, low phase noise and fast synchronization in wide frequency range. The system is developed and tested on Spartan 3E FPGA by Xilinx.
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带单参考频率振荡器的全数字锁相环
本文设计了全数字锁相环。开发并测试了一种组合倍频器,以实现仅使用一个低频参考振荡器的完全集成系统。采用自适应比例积分调节,在宽频率范围内保证高稳定性、低相位噪声和快速同步。该系统在赛灵思公司的Spartan 3E FPGA上进行了开发和测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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