Neural net implementation on single-chip digital signal processor

Abstract

Madaline rule II (MRII) and back-propagation (BP) algorithms have been implemented on a digital signal processor (DSP). Two kinds of modifications of MRII are proposed: a tree search for the best up-to-two-order combinations of neurons in a randomly chosen layer and an efficient way of setting the desired response value for the least-mean-square (LMS) adaptation of the neurons. A sigmoid table lookup function and some details of the implementation of the BP algorithm are presented. Perceptron span limitations, as the maximum number of neurons per layer, and processing times are given for both systems. This gives a good understanding of the general requirements for the implementation of perceptrons on DSP, such as memory space, data flow, and multiplier functional needs. The training behavior of the BP program on DSP is analyzed with reference to the example of handwritten character recognition. In spite of the low accuracy of DSP floating-point data, the perceptron simulation on DSP shows better results than a C-simulation program on a personal computer.<>