K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, Y. Hayashi
{"title":"Process design methodology for via-shape-controlled, copper dual-damascene interconnects in low-k organic film","authors":"K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, Y. Hayashi","doi":"10.1109/IEDM.2000.904305","DOIUrl":null,"url":null,"abstract":"By dual hard mask (dHM) process combined with sidewall-hardening etching step, copper dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers under the trench. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has low via resistance such as 0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via while keeping the large tolerance of misalignment in via/trench, appreciable for 0.1 /spl mu/m-generation CMOS ULSIs.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2000.904305","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
By dual hard mask (dHM) process combined with sidewall-hardening etching step, copper dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers under the trench. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has low via resistance such as 0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via while keeping the large tolerance of misalignment in via/trench, appreciable for 0.1 /spl mu/m-generation CMOS ULSIs.