Chip-level and Input/Output Interconnects for Gigascale SOCs: Limits and Opportunities

Abstract

Introduction Interconnects are considered as one of the grandest challenges facing gigaand tera-scale integration (GSI/TSI). One may define interconnects as media for energy transfer in a GSI chip including electrical, thermal and potentially optical energies (power, signal and thermal interconnects). At the chip level, interconnects have become the major component in the delay of critical paths, are the largest source of power dissipation, generate crosstalk and power supply noise, and cause reliability problems due to electromigration and fragile low-k materials. Additional constraints on the performance of GSI/TSI chips are imposed by today's inferior heat removal technologies (thermal interconnects), inadequate off-chip Input/Output (I/0) bandwidth and the challenges of delivering hundreds of amperes of power supply current with ever decreasing noise margins. In this tutorial, quantitative models will be presented for the physical limits of interconnects and promising solutions for addressing the 'interconnect problem' will be discussed.