0.65 V integrable electronic realisation of integer- and fractional-order Hindmarsh-Rose neuron model using companding technique

F. A. Khanday, Mohammad Rafiq Dar, N. A. Kant, J. Rosselló, C. Psychalinos
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引用次数: 13

Abstract

Some neurons like neocortical pyramidal neurons adapt with multiple time-scales, which is consistent with fractional-order differentiation. The fractional-order neuron models are therefore believed to portray the firing rate of neurons more accurately than their integer-order models. It has been studied that as the fractional order of differentiator and integrator involved in the neuron model decreases, bursting frequency of the neurons increases. The opposite effect has been observed on increasing the external excitation. In this study, integer- and fractional-order Hindmarsh–Rose (HR) neuron models have been implemented using sinh companding technique. Besides, the application of the HR neuron model in a simple network of two neurons has also been considered. The designs offer a low-voltage and low-power implementation along with the electronic tunability of the performance characteristics. Due to the use of only metal-oxide semiconductor (MOS) transistors and grounded capacitors, the proposed implementation can be integrated in chip form. On comparing with existing implementations, the implemented fractional-order and integer-order models show a better performance in terms of power consumption, supply voltage, order and flexibility. The performance of the circuits has been verified using 130 nm complementary MOS (CMOS) technology process provided by Austrian Micro Systems using HSPICE simulation software.
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基于扩展技术的整数阶和分数阶Hindmarsh-Rose神经元模型的0.65 V可积电子实现
一些神经元如新皮层锥体神经元适应多时间尺度,这与分数阶分化是一致的。因此,分数阶神经元模型被认为比整数阶模型更准确地描述了神经元的放电速率。研究表明,随着神经元模型中微分器和积分器分数阶的降低,神经元的破裂频率增加。在增加外部激励时,观察到相反的效果。在本研究中,采用sinh扩展技术实现了整数阶和分数阶Hindmarsh-Rose (HR)神经元模型。此外,还考虑了HR神经元模型在简单双神经元网络中的应用。该设计提供了低电压和低功耗的实现以及性能特征的电子可调性。由于仅使用金属氧化物半导体(MOS)晶体管和接地电容器,所提出的实现可以集成在芯片形式。与现有的实现方法相比,所实现的分数阶和整阶模型在功耗、供电电压、顺序和灵活性方面表现出更好的性能。采用奥地利微系统公司提供的130 nm互补MOS (CMOS)工艺,利用HSPICE仿真软件对电路的性能进行了验证。
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