Jérôme Folla Kamdem, M. Crespo, W. T. Evariste, M. Bhuiyan, A. Cicuttin, E. Bernard, M. Reaz
Department of Physics, Laboratory of Energy, Electrical and Electronics Systems, University of Yaoundé I, Yaoundé, Cameroon Multidisciplinary Laboratory (MLAB), International Centre for Theoretical Physics (ICTP), Trieste, Italy Department of Physics, Laboratory of Electronics and Automatics, University of Douala, Douala, Cameroon Electrical and Electronics Engineering, Xiamen University Malaysia, Sepang, Selangor, Malaysia Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia
{"title":"A low-offset low-power and high-speed dynamic latch comparator with a preamplifier-enhanced stage","authors":"Jérôme Folla Kamdem, M. Crespo, W. T. Evariste, M. Bhuiyan, A. Cicuttin, E. Bernard, M. Reaz","doi":"10.1049/cds2.12008","DOIUrl":"https://doi.org/10.1049/cds2.12008","url":null,"abstract":"Department of Physics, Laboratory of Energy, Electrical and Electronics Systems, University of Yaoundé I, Yaoundé, Cameroon Multidisciplinary Laboratory (MLAB), International Centre for Theoretical Physics (ICTP), Trieste, Italy Department of Physics, Laboratory of Electronics and Automatics, University of Douala, Douala, Cameroon Electrical and Electronics Engineering, Xiamen University Malaysia, Sepang, Selangor, Malaysia Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi, Selangor, Malaysia","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121306916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ashish Sachdeva, ECE Department, GLA University, Mathura, India. Email: er.ashishsachdeva@gmail.com Funding Information The authors have no relevant financial or non‐ financial/ Funding interests to disclose. Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78� and 2.326� in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03� in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.
{"title":"Design of 10T SRAM cell with improved read performance and expanded write margin","authors":"Ashish Sachdeva, V. Tomar","doi":"10.1049/cds2.12006","DOIUrl":"https://doi.org/10.1049/cds2.12006","url":null,"abstract":"Ashish Sachdeva, ECE Department, GLA University, Mathura, India. Email: er.ashishsachdeva@gmail.com Funding Information The authors have no relevant financial or non‐ financial/ Funding interests to disclose. Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78� and 2.326� in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03� in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134629862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qing-Hao Hu, Wensheng Zhao, Kai Fu, Dawei Wang, Gaofeng Wang
This study investigates the possibility of the carbon nanotube (CNT) ‐ based through ‐ silicon vias (TSVs) for improving power integrity of 3 ‐ D integrated circuits (3 ‐ D ICs). The circuit model is developed for 2 ‐ bit CNT TSV and validated through the full ‐ wave electromagnetic simulator HFSS simulations. The 2 ‐ bit CNT TSV is applied to power distribution networks (PDNs) by combining the validated equivalent ‐ circuit model and that TSV ‐ based PDN impedance is compared with the traditional one. By virtue of the large capacitance and low inductance of the 2 ‐ bit CNT TSV, the PDN impedance of the 3 ‐ D IC can be suppressed significantly and the anti ‐ resonant frequency can be increased.
{"title":"On the applicability of two-bit carbon nanotube through-silicon via for power distribution networks in 3-D integrated circuits","authors":"Qing-Hao Hu, Wensheng Zhao, Kai Fu, Dawei Wang, Gaofeng Wang","doi":"10.1049/cds2.12010","DOIUrl":"https://doi.org/10.1049/cds2.12010","url":null,"abstract":"This study investigates the possibility of the carbon nanotube (CNT) ‐ based through ‐ silicon vias (TSVs) for improving power integrity of 3 ‐ D integrated circuits (3 ‐ D ICs). The circuit model is developed for 2 ‐ bit CNT TSV and validated through the full ‐ wave electromagnetic simulator HFSS simulations. The 2 ‐ bit CNT TSV is applied to power distribution networks (PDNs) by combining the validated equivalent ‐ circuit model and that TSV ‐ based PDN impedance is compared with the traditional one. By virtue of the large capacitance and low inductance of the 2 ‐ bit CNT TSV, the PDN impedance of the 3 ‐ D IC can be suppressed significantly and the anti ‐ resonant frequency can be increased.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127323881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, the authors propose a work function engineered (WFE) triple metal (TM) tunnel field ‐ effect transistor (TFET) device, which exhibits lower subthreshold slope (SS) and better on to off current ratio in comparison with conventional double gate TFET and dual metal TFET device. An analytical model is formulated to study the performance of the proposed device. A simulation ‐ based study of these TFET devices has been carried out with the help of 2D TCAD (Technology Computer Aided Design) Sentaurus device simulator for different channel length values in order to validate our proposed mathematical model. The source side n þ pocket in the proposed triple metal (TM) TFET device enhances tunnelling probability thus increasing on current and off current is controlled by another n ‐ pocket near drain side. Significantly lower subthreshold slope (less than 10 mV/decade), high transconductance (in the order of 10 (cid:0) 4 S/μm), low energy ‐ delay product (24.601 fJ ‐ ns/μm) obtained for TM WFE TFET makes this device more suitable for digital logic and RF (Radio Frequency) application.
{"title":"Analytical model and simulation-based analysis of a work function engineered triple metal tunnel field-effect transistor device showing excellent device performance","authors":"R. Bose, J. Roy","doi":"10.1049/cds2.12009","DOIUrl":"https://doi.org/10.1049/cds2.12009","url":null,"abstract":"In this study, the authors propose a work function engineered (WFE) triple metal (TM) tunnel field ‐ effect transistor (TFET) device, which exhibits lower subthreshold slope (SS) and better on to off current ratio in comparison with conventional double gate TFET and dual metal TFET device. An analytical model is formulated to study the performance of the proposed device. A simulation ‐ based study of these TFET devices has been carried out with the help of 2D TCAD (Technology Computer Aided Design) Sentaurus device simulator for different channel length values in order to validate our proposed mathematical model. The source side n þ pocket in the proposed triple metal (TM) TFET device enhances tunnelling probability thus increasing on current and off current is controlled by another n ‐ pocket near drain side. Significantly lower subthreshold slope (less than 10 mV/decade), high transconductance (in the order of 10 (cid:0) 4 S/μm), low energy ‐ delay product (24.601 fJ ‐ ns/μm) obtained for TM WFE TFET makes this device more suitable for digital logic and RF (Radio Frequency) application.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133828297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Charge ‐ pump phase ‐ locked loop (CP ‐ PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all ‐ digital built ‐ in self ‐ test structure of CP ‐ PLL especially suitable for low ‐ cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP ‐ PLL under test. It reduces the requirement of additional external test clocks and high ‐ performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.
{"title":"All-digital built-in self-test scheme for charge-pump phase-locked loops","authors":"Lanhua Xia, Jifei Tang","doi":"10.1049/cds2.12000","DOIUrl":"https://doi.org/10.1049/cds2.12000","url":null,"abstract":"Charge ‐ pump phase ‐ locked loop (CP ‐ PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all ‐ digital built ‐ in self ‐ test structure of CP ‐ PLL especially suitable for low ‐ cost production tests when I/O port resources are limited is proposed. The structure is simple and easily implemented with just a few DFFs, MUXs and some existing circuits in CP ‐ PLL under test. It reduces the requirement of additional external test clocks and high ‐ performance test equipment, which decreases the test cost of the whole integrated circuits. Combined with the proposed calibration technique, it eliminates the effect of uncertain initial value of voltage controlled oscillator input voltage on the fault coverage. Thus, the reliability of test results is also increased. Experiment results demonstrate the effectiveness of the proposed scheme with high fault coverage of 99.16%. In addition, the physical chip design is presented to show low area overhead of 1.37%.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132728736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-10DOI: 10.1049/IET-CDS.2019.0013
Sung-hwan Lee, I. Kwon
This article proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When an undershoot or overshoot voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. An adaptively biased single-stage error amplifier with a cross-coupled pair is used to improve stability without external capacitors at low quiescent current consumption. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3% and the settling time by 55.5% without consuming additional quiescent current.
{"title":"Fast transient low-dropout regulator with undershoot and settling time reduction technique","authors":"Sung-hwan Lee, I. Kwon","doi":"10.1049/IET-CDS.2019.0013","DOIUrl":"https://doi.org/10.1049/IET-CDS.2019.0013","url":null,"abstract":"This article proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When an undershoot or overshoot voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. An adaptively biased single-stage error amplifier with a cross-coupled pair is used to improve stability without external capacitors at low quiescent current consumption. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3% and the settling time by 55.5% without consuming additional quiescent current.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120648001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1049/IET-CDS.2018.5485
S. Rekha, V. M. Harishchandra, T. Laxminidhi
The authors propose circuit techniques to implement integrated continuous-time filters for low voltage and low power applications. A fourth order G m-C filter and a fifth order active-RC Chebyshev filter are used as test vehicles to validate the ideas. Basic building blocks are bulk driven transconductors. G m-C filter and active-RC filter offer bandwidth of 1 MHz and 750 kHz, respectively while exhibiting a good figure of merit thus ensuring that the designs are energy efficient. Both the filters, fabricated on the same chip in 180 nm CMOS technology, operate on 0.5 V power supply. They offer a dynamic range of 45 and 46.6 dB, respectively.
{"title":"Ultra-low voltage, power efficient continuous-time filters in 180 nm CMOS technology","authors":"S. Rekha, V. M. Harishchandra, T. Laxminidhi","doi":"10.1049/IET-CDS.2018.5485","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5485","url":null,"abstract":"The authors propose circuit techniques to implement integrated continuous-time filters for low voltage and low power applications. A fourth order G m-C filter and a fifth order active-RC Chebyshev filter are used as test vehicles to validate the ideas. Basic building blocks are bulk driven transconductors. G m-C filter and active-RC filter offer bandwidth of 1 MHz and 750 kHz, respectively while exhibiting a good figure of merit thus ensuring that the designs are energy efficient. Both the filters, fabricated on the same chip in 180 nm CMOS technology, operate on 0.5 V power supply. They offer a dynamic range of 45 and 46.6 dB, respectively.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120287049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1049/IET-CDS.2019.0130
Pramod Patali, S. Kassim
A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add–multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power–delay product and area–delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.
{"title":"High throughput FIR filter architectures using retiming and modified CSLA based adders","authors":"Pramod Patali, S. Kassim","doi":"10.1049/IET-CDS.2019.0130","DOIUrl":"https://doi.org/10.1049/IET-CDS.2019.0130","url":null,"abstract":"A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add–multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power–delay product and area–delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"119404380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-07DOI: 10.1049/IET-CDS.2018.5617
Madhusmita Panda, S. Patnaik, A. K. Mal, Sumalya Ghosh
In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.
{"title":"Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms","authors":"Madhusmita Panda, S. Patnaik, A. K. Mal, Sumalya Ghosh","doi":"10.1049/IET-CDS.2018.5617","DOIUrl":"https://doi.org/10.1049/IET-CDS.2018.5617","url":null,"abstract":"In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"118732781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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