All-digital delay line-based time difference amplifier in 65 nm CMOS technology

Abstract

Time-to-digital converter (TDC) is one of the important blocks in most of the digital systems that need to have high resolution. Time difference amplifier (TDA) is used in TDC for increasing the resolution. In this study, an all-digital TDA is proposed. The proposed TDA uses the delay lines with difference delay for amplifying. The proposed circuit is designed and simulated in 65 nm CMOS technology and has a gain of ten and a chip area of about 0.003 mm2. The calculated maximum gain error is 5%. The proposed TDA consumes 0.94 mW power under 1.1 V supply voltage.