A general class of zero- or minimum-delay fractional rate change circuits

Abstract

Rate changing occurs whenever sequences of data undergo transformations in rate without undergoing a change in the order of sequence. When the ratio of transformation is not an integer, fractional rate changes are necessary. These are generally, a prerequisite for the time-compression multiplexing mode of data transmission. Zero or minimal delay is a desirable characteristic, for example, in reducing the annoyance from the far-end echo whenever voice is encoded and transmitted. Conventional fractional rate changing entails an inherent delay in the rate change circuits. Segmenting shift registers reduces the delay of the last bit without completely eliminating it, unless the shift-register length is reduced to one bit. In this paper, a method of partitioning the shift registers by logarithmic counts is developed to reduce the complexity of the gating and the counting circuits. Zero last-bit delays are attainable in all cases where the rate increase is greater than two or, conversely, the rate reduction is less than half. For the remaining cases, the compromise between circuit complexity and the last-bit delay is outlined.