Binary multiplication based on single electron tunneling

C. Lageweg, S. Cotofana, S. Vassiliadis
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引用次数: 7

Abstract

This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.
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基于单电子隧穿的二进制倍增
这项工作研究了基于单电子隧道的16位和32位树乘法器的实现,这些乘数器根据单电子编码逻辑范式运行。首先,我们提出了一组基本组件(13/2计数器,7/3计数器)的实现,并通过仿真验证了它们。其次,我们提出了基于这些元件的16位和32位树乘法器,并从面积、延迟和功耗方面分析了这些乘法器。第三,我们研究了32位乘法器的替代设计,并得出结论,基于7/3计数器的实现不如预期的有效。因此,我们提出了改进的7/3计数器,并评估了这些新设计对16位和32位乘法器的面积、延迟和功耗的影响。
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