Pub Date : 2004-10-18DOI: 10.1109/ASAP.2004.1342470
Ljiljana Dilparic, D. Arvind
This work presents a network-based asynchronous architecture that improves the physical-level security of cryptographic devices to known side-channel attacks. This is achieved by decorrelating power consumption measurements by exploiting parallel execution and randomised data-forwarding over a network of functional units. Instructions execute in parallel and forward register values between them, thereby avoiding the register bank. A secret-sharing scheme is used in data-forwarding to remove the effect of sending critical register values through the network, which does not significantly degrade performance and has a positive effect of increasing the noise due to network activity. The simulation results show that both the security threshold and the performance are improved, and the network-based architecture is more robust to differential power analysis when compared to the asynchronous pipelined architecture.
{"title":"Design and evaluation of a network-based architecture for cryptographic devices","authors":"Ljiljana Dilparic, D. Arvind","doi":"10.1109/ASAP.2004.1342470","DOIUrl":"https://doi.org/10.1109/ASAP.2004.1342470","url":null,"abstract":"This work presents a network-based asynchronous architecture that improves the physical-level security of cryptographic devices to known side-channel attacks. This is achieved by decorrelating power consumption measurements by exploiting parallel execution and randomised data-forwarding over a network of functional units. Instructions execute in parallel and forward register values between them, thereby avoiding the register bank. A secret-sharing scheme is used in data-forwarding to remove the effect of sending critical register values through the network, which does not significantly degrade performance and has a positive effect of increasing the noise due to network activity. The simulation results show that both the security threshold and the performance are improved, and the network-based architecture is more robust to differential power analysis when compared to the asynchronous pipelined architecture.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122313815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, E. Sha
This work develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (switching-activity minimization loop scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.
{"title":"Switching-activity minimization on instruction-level loop for VLIW DSP applications","authors":"Z. Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, E. Sha","doi":"10.1109/ASAP.2004.10023","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10023","url":null,"abstract":"This work develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (switching-activity minimization loop scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127815274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded systems. In this framework we perform the synthesis under several constraints while optimizing for a set of objectives. We allow the designer to fully control the performance evaluation process, constraint parameters, and optimization goals. Once the synthesis is performed, we provide the designer a non-dominated set (Pareto front) of implementations on streamlined architectures that are in general heterogeneous and distributed. We also employ two different techniques, namely clustering and parallelization, to reduce the complexity of the solution space and expedite the search. The experimental results demonstrate the effectiveness of the CHARMED framework in computing efficient co-synthesis solutions within a reasonable amount of time.
{"title":"CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems","authors":"V. Kianzad, S. Bhattacharyya","doi":"10.1109/ASAP.2004.10027","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10027","url":null,"abstract":"We present a modular co-synthesis framework called CHARMED that solves the problem of hardware-software co-synthesis of periodic, multi-mode, distributed, embedded systems. In this framework we perform the synthesis under several constraints while optimizing for a set of objectives. We allow the designer to fully control the performance evaluation process, constraint parameters, and optimization goals. Once the synthesis is performed, we provide the designer a non-dominated set (Pareto front) of implementations on streamlined architectures that are in general heterogeneous and distributed. We also employ two different techniques, namely clustering and parallelization, to reduce the complexity of the solution space and expedite the search. The experimental results demonstrate the effectiveness of the CHARMED framework in computing efficient co-synthesis solutions within a reasonable amount of time.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124405594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Schulte, K. Chirca, J. Glossner, Haoran Wang, S. Mamidi, P. Balzola, S. Vassiliadis
We present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130 nm CMOS technology. At 1.2 V and 25 C, the 32-bit adder has a critical path delay of 921 ps and average power dissipation normalized to 600 MHz operation of 0.786 mW. We also present a technique to quickly perform saturating addition, which is useful in a variety of digital signal processing and multimedia applications. Our technique for fast saturation is based on techniques for carry select addition and works particularly well when the input and output operands can have different formats. A 40-bit carry skip adder that uses our technique for fast saturation has critical path delays of 1149 ps in 130 nm technology at 1.2 V and 25 C and 560 ps in 90nm technology at 1.0 V and 25 C. The 40-bit adder's average power dissipation normalized to 600 MHz operation is 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.
{"title":"A low-power carry skip adder with fast saturation","authors":"M. Schulte, K. Chirca, J. Glossner, Haoran Wang, S. Mamidi, P. Balzola, S. Vassiliadis","doi":"10.1109/ASAP.2004.10038","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10038","url":null,"abstract":"We present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipation are reduced by dividing the adder into variable-sized blocks that balance the delay of inputs to the carry chain. This grouping reduces active power by minimizing extraneous glitches and transitions. Each block also uses highly optimized complementing carry look-ahead logic to reduce delay. Compared to previous designs, the adder architecture decreases power consumption by reducing the number of transistors, logic levels, and glitches. A 32-bit carry skip adder design that uses our approach has been implemented in 130 nm CMOS technology. At 1.2 V and 25 C, the 32-bit adder has a critical path delay of 921 ps and average power dissipation normalized to 600 MHz operation of 0.786 mW. We also present a technique to quickly perform saturating addition, which is useful in a variety of digital signal processing and multimedia applications. Our technique for fast saturation is based on techniques for carry select addition and works particularly well when the input and output operands can have different formats. A 40-bit carry skip adder that uses our technique for fast saturation has critical path delays of 1149 ps in 130 nm technology at 1.2 V and 25 C and 560 ps in 90nm technology at 1.0 V and 25 C. The 40-bit adder's average power dissipation normalized to 600 MHz operation is 0.928 mW in 130 nm technology and 0.335 mW in 90 nm technology.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.
{"title":"Binary multiplication based on single electron tunneling","authors":"C. Lageweg, S. Cotofana, S. Vassiliadis","doi":"10.1109/ASAP.2004.10019","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10019","url":null,"abstract":"This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120824254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a significant extension of the quantified equation based algorithm class of piecewise regular algorithms. The main contributions of the following paper are: the class of piecewise regular algorithms are extended by allowing run-time dependent conditionals; a mixed integer linear program is given to derive optimal schedules of the novel class we call dynamic piecewise regular algorithms; and in order to achieve highest performance, we present a speculative scheduling approach. The results are applied to an illustrative example.
{"title":"Resource constrained and speculative scheduling of an algorithm class with run-time dependent conditionals","authors":"Frank Hannig, J. Teich","doi":"10.1109/ASAP.2004.10029","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10029","url":null,"abstract":"We present a significant extension of the quantified equation based algorithm class of piecewise regular algorithms. The main contributions of the following paper are: the class of piecewise regular algorithms are extended by allowing run-time dependent conditionals; a mixed integer linear program is given to derive optimal schedules of the novel class we call dynamic piecewise regular algorithms; and in order to achieve highest performance, we present a speculative scheduling approach. The results are applied to an illustrative example.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129926605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The integrated circuit, manufactured by optical lithography, has driven the computer revolution for four decades. If we are to continue to build complex systems of ever-smaller components, we must find a new technology that will allow massively parallel construction of electronic circuits at the atomic scale. To do so we must develop both the molecular electronics building blocks and CAD algorithms for such a reconfigurable technology.
{"title":"Defect-tolerant molecular electronics","authors":"P. Kuekes","doi":"10.1109/ASAP.2004.18","DOIUrl":"https://doi.org/10.1109/ASAP.2004.18","url":null,"abstract":"The integrated circuit, manufactured by optical lithography, has driven the computer revolution for four decades. If we are to continue to build complex systems of ever-smaller components, we must find a new technology that will allow massively parallel construction of electronic circuits at the atomic scale. To do so we must develop both the molecular electronics building blocks and CAD algorithms for such a reconfigurable technology.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130473147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents an algorithm and architecture that integrates modular division and multiplication in both GF(p) and GF(2/sup n/) fields (unified). The algorithm is based on the extended binary GCD algorithm for modular division and on the Montgomery's method for modular multiplication. For the division operation, the proposed algorithm uses a counter to keep track of the difference between two field elements and this way eliminate the need for comparisons which are usually expensive and time-consuming. The proposed architecture efficiently supports all the operations in the algorithm and uses carry-save unified adders for reduced critical path delay, making the proposed architecture faster than other previously proposed designs. Experimental results using synthesis for AMI 0.5 /spl mu/m CMOS technology are shown and compared with other dividers and multipliers.
本文提出了一种在GF(p)和GF(2/sup n/)域(统一)中集成模块化除法和乘法的算法和体系结构。该算法基于模除法的扩展二进制GCD算法和模乘法的Montgomery方法。对于除法操作，建议的算法使用计数器来跟踪两个字段元素之间的差异，这样就消除了通常昂贵且耗时的比较的需要。该架构有效地支持算法中的所有操作，并使用免进位的统一加法器来减少关键路径延迟，使该架构比其他先前提出的设计更快。给出了AMI 0.5 /spl μ m CMOS技术合成的实验结果，并与其他分频和乘法器进行了比较。
{"title":"An algorithm and hardware architecture for integrated modular division and multiplication in GF(p) and GF(2/sup n/)","authors":"L. Tawalbeh, A. Tenca","doi":"10.1109/ASAP.2004.10034","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10034","url":null,"abstract":"This work presents an algorithm and architecture that integrates modular division and multiplication in both GF(p) and GF(2/sup n/) fields (unified). The algorithm is based on the extended binary GCD algorithm for modular division and on the Montgomery's method for modular multiplication. For the division operation, the proposed algorithm uses a counter to keep track of the difference between two field elements and this way eliminate the need for comparisons which are usually expensive and time-consuming. The proposed architecture efficiently supports all the operations in the algorithm and uses carry-save unified adders for reduced critical path delay, making the proposed architecture faster than other previously proposed designs. Experimental results using synthesis for AMI 0.5 /spl mu/m CMOS technology are shown and compared with other dividers and multipliers.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128858841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. We discuss a scheduling algorithm for distributing IPSec packet processing over the CPU with a software implementation of the cryptographic algorithms considered and multiple cryptographic accelerators. High-level simulations and the related results are provided to show the properties of the algorithm. Some architectural improvements suitable to better exploit this scheduling algorithm are also presented.
{"title":"A packet scheduling algorithm for IPSec multi-accelerator based systems","authors":"F. Castanier, A. Ferrante, V. Piuri","doi":"10.1109/ASAP.2004.10016","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10016","url":null,"abstract":"IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. We discuss a scheduling algorithm for distributing IPSec packet processing over the CPU with a software implementation of the cryptographic algorithms considered and multiple cryptographic accelerators. High-level simulations and the related results are provided to show the properties of the algorithm. Some architectural improvements suitable to better exploit this scheduling algorithm are also presented.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126236328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fault detection in encryption algorithms is gaining in importance since fault attacks may compromise even recently developed cryptosystems. We analyze the different operations used by various symmetric ciphers and propose possible detection codes and frequency of checking. Several examples (i.e., AES, RC5, DES and IDEA) are presented to illustrate our analysis.
{"title":"Detecting faults in four symmetric key block ciphers","authors":"L. Breveglieri, I. Koren, P. Maistri","doi":"10.1109/ASAP.2004.10035","DOIUrl":"https://doi.org/10.1109/ASAP.2004.10035","url":null,"abstract":"Fault detection in encryption algorithms is gaining in importance since fault attacks may compromise even recently developed cryptosystems. We analyze the different operations used by various symmetric ciphers and propose possible detection codes and frequency of checking. Several examples (i.e., AES, RC5, DES and IDEA) are presented to illustrate our analysis.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116092785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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