Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors

Abstract

The objective of the research presented in this talk is to investigate the relative importance of errors in a modern microprocessor based on the impact that they incur on the execution of typical workload. Such information can prove immensely useful in allocating resources to enhance on-line testability and error resilience through concurrent error detection/correction methods. Indeed, modern microprocessors exhibit an inherent effectiveness in suppressing a significant percentage of errors and preventing them from interfering with correct program execution (i.e. application-level masking). Therefore, understanding and leveraging the correlation between low-level errors and their instruction-level impact is crucial towards developing cost-effective mitigation methods. To this end, I will first report on an extensive fault simulation infrastructure that we developed around a superscalar, dynamicallyscheduled, out-of-order, Alpha-like microprocessor, which supports execution of SPEC2000 integer benchmarks and enables the aforementioned correlation study. Then, I will demonstrate the utility of this information in developing cost-effective concurrent error detection and soft error mitigation methods for modern microprocessors. Finally, I will discuss the application of workload-cognizant impact analysis in identifying and dealing with faults that do not affect functional correctness but simply slow down program execution in modern microprocessors (i.e. performance faults).