Serial/Parallel architectures for area-efficient vector multiplication

Abstract

The use of standard-part multiply/accumulators in digital signal processing is often in the computation of vector products. In the realm of custom VLSI, direct computation of vector products can result in area savings over classical multiply/accumulate methods. A methodology is presented for composition of VLSI architectures for direct vector multiplication, based on three fundamental computational elements. These are register, data selecter, and carry-save add-shift (CSAS) computer. The CSAS computer is a linear array of gated carry-save adders which performs shifting accumulation of partial results. Two's complement serial/parallel carry-save accumulation provides performance, while the use of symmetric-coded distributed arithmetic eliminates redundant computation to effect area-savings.