Design and Implementation of an Efficient Buffer Management System for Network on Chip Routers

Vipul Bhatnagar, Saket Kumar, M. Pandey, S. Pandey
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Abstract

The paper presents an efficient first in first out (FIFO) buffer for use in network on chip routers for efficient management of data flow. Further we have designed a heterogeneous router using the efficient FIFO buffer, in which each channel can have a different buffer size. Even the FIFO of a particular channel is full it can borrow more buffer length from neighbouring channels. In this new architecture read and write operations are managed by the FIFO and channel itself, thus reducing the circuitry and making it a high speed router.
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片上路由器高效缓冲管理系统的设计与实现
本文提出了一种高效的先进先出(FIFO)缓冲器,用于片上网络路由器,以实现对数据流的有效管理。此外,我们还设计了一个使用高效FIFO缓冲区的异构路由器,其中每个通道可以有不同的缓冲区大小。即使某个通道的FIFO已经满了,它也可以从邻近的通道借用更多的缓冲区长度。在这种新架构中,读写操作由FIFO和通道本身管理,从而减少了电路并使其成为高速路由器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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