A Novel SAR Fast-Locking Digital PLL: SPICE Modeling and Simulations

Abstract

A novel fast-locking DPLL based on the Successive-Approximation Register (SAR) is presented and modeled using SPICE. The DPLL has two distinct stages of operation: 1) A coarse-tuning stage which employs frequency tracking to bring the VCO and reference frequencies close to each other and 2) a fine tuning stage which uses conventional phase tracking to achieve a complete lock. The coarse-tuning stage consists of a frequency comparator, a SAR, and a D/A converter (DAC). The architecture of the SAR DPLL has been designed and simulated in 250nm SPICE. The fast-locking DPLL was found to be 1.5 to 3 times faster than the conventional DPLL.