Scalability of PCMO-based resistive switch device in DSM technologies

Yiran Chen, Wei Tian, Hai Helen Li, Xiaobin Wang, Wenzhong Zhu
{"title":"Scalability of PCMO-based resistive switch device in DSM technologies","authors":"Yiran Chen, Wei Tian, Hai Helen Li, Xiaobin Wang, Wenzhong Zhu","doi":"10.1109/ISQED.2010.5450447","DOIUrl":null,"url":null,"abstract":"This work systematically explores the relationship between the resistive switching properties of Pr0.7Ca0.3MnO3 (PCMO) thin film element and its geometry dimensions in deep submicron (DSM) technologies. A series of PCMO-based resistive switch devices (RSDs) with different geometry sizes were fabricated. Our E-test results show that by reducing the PCMO layer thickness from the normal value of about 200nm to 30nm, a low switching voltage (within ±2.5V) can be achieved. The reduction of PCMO layer thickness does not incur visible impact on device reliability: no significant degradation of two resistance states was observed after 1500 programming cycles. Based on the extrapolation from the measured electrical parameters of PCMO-based devices, we analyzed the design requirements of PCMO-based resistive memory with different cell structures in sub-100nm technologies. Our simulations show that one-transistor-one-RSD (1T1R) cell structure can be successfully scaled down to 22nm technology node. However, the scaling of one-non-ohmicdevice-one-RSD (1N1R) cell structure is significantly limited by the low driving ability of current non-ohmic device technology.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"106 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 11th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2010.5450447","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

This work systematically explores the relationship between the resistive switching properties of Pr0.7Ca0.3MnO3 (PCMO) thin film element and its geometry dimensions in deep submicron (DSM) technologies. A series of PCMO-based resistive switch devices (RSDs) with different geometry sizes were fabricated. Our E-test results show that by reducing the PCMO layer thickness from the normal value of about 200nm to 30nm, a low switching voltage (within ±2.5V) can be achieved. The reduction of PCMO layer thickness does not incur visible impact on device reliability: no significant degradation of two resistance states was observed after 1500 programming cycles. Based on the extrapolation from the measured electrical parameters of PCMO-based devices, we analyzed the design requirements of PCMO-based resistive memory with different cell structures in sub-100nm technologies. Our simulations show that one-transistor-one-RSD (1T1R) cell structure can be successfully scaled down to 22nm technology node. However, the scaling of one-non-ohmicdevice-one-RSD (1N1R) cell structure is significantly limited by the low driving ability of current non-ohmic device technology.
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DSM技术中基于pcmo的阻性开关器件的可扩展性
本文系统地探讨了深亚微米(DSM)技术中Pr0.7Ca0.3MnO3 (PCMO)薄膜元件的电阻开关特性与其几何尺寸之间的关系。制备了一系列不同几何尺寸的基于pcmo的电阻开关器件(rsd)。我们的E-test结果表明,通过将PCMO层厚度从正常值约200nm减小到30nm,可以实现低开关电压(±2.5V以内)。PCMO层厚度的减少不会对器件可靠性产生明显的影响:在1500个编程周期后,没有观察到两种电阻状态的显著退化。在对基于pcmo器件的电参数进行外推的基础上,分析了亚100nm工艺下不同单元结构的pcmo电阻式存储器的设计要求。我们的模拟表明,单晶体管-单rsd (1T1R)电池结构可以成功地缩小到22nm技术节点。然而,当前非欧姆器件技术驱动能力较低,严重限制了单非欧姆器件-单rsd (1N1R)电池结构的扩展。
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