Aarti Rathi, M. Kumar, Jayhind K. Verma, H. S. Jatana, Y. Chauhan, A. Dixit
{"title":"Modeling of $0.18\\mu\\mathrm{m}$ RF Bulk and SOI Planar MOSFETs using Industry Standard BSIM Models","authors":"Aarti Rathi, M. Kumar, Jayhind K. Verma, H. S. Jatana, Y. Chauhan, A. Dixit","doi":"10.1109/icee50728.2020.9776772","DOIUrl":null,"url":null,"abstract":"In this paper, parameters are extracted for scalable DC and RF models of bulk & SOI MOSFETs using industry-standard models: BSIM-BULK and BSIM-SOI respectively. These made-in-India devices were fabricated by Semiconductor Laboratory, Chandigarh using $0.18\\mu\\mathrm{m}$ CMOS technology. One of the main reasons for choosing BSIM BULK over BSIM4 model for analog and RF applications is to ensure continuous drain current and its higher order derivatives w.r.t. bias voltages. This is not possible in the threshold voltage based BSIM3 and BSIM4 models due to asymmetry around $\\text{Vds}=0\\ \\mathrm{V}$. BSIM BULK being a charge-based and body reference model does not suffer from this issue. The models show a high degree of correlation across geometries, biases, and frequencies. We have simulated circuits using the extracted RF Bulk and RF SOI FET models, such as the ring oscillator and Low Noise Amplifier. Performance of Bulk and SOI circuits is compared in terms of speed and noise figure.","PeriodicalId":436884,"journal":{"name":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","volume":"43 16","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 5th IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icee50728.2020.9776772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, parameters are extracted for scalable DC and RF models of bulk & SOI MOSFETs using industry-standard models: BSIM-BULK and BSIM-SOI respectively. These made-in-India devices were fabricated by Semiconductor Laboratory, Chandigarh using $0.18\mu\mathrm{m}$ CMOS technology. One of the main reasons for choosing BSIM BULK over BSIM4 model for analog and RF applications is to ensure continuous drain current and its higher order derivatives w.r.t. bias voltages. This is not possible in the threshold voltage based BSIM3 and BSIM4 models due to asymmetry around $\text{Vds}=0\ \mathrm{V}$. BSIM BULK being a charge-based and body reference model does not suffer from this issue. The models show a high degree of correlation across geometries, biases, and frequencies. We have simulated circuits using the extracted RF Bulk and RF SOI FET models, such as the ring oscillator and Low Noise Amplifier. Performance of Bulk and SOI circuits is compared in terms of speed and noise figure.