A 40 Gb/s Optical Receiver in 80-nm CMOS for Short-Distance High-Density Interconnects

Abstract

An optical receiver for short-range optical data communication up to 40 Gb/s is presented. The optimum number of limiting amplifier (LA) stages is calculated to achieve a large gain-bandwidth product. The receiver features an electrical transimpedance gain of 91.4 dBOmega and a bandwidth of 19.2 GHz. For the free-space optical measurements (lambda=1550nm) an InGaAs/lnP photo diode (PD) and the CMOS receiver chip were placed and bonded on a test substrate. At 40 Gb/s an open eye at the output of the receiver is shown at an optical input power of -4.6 dBni. Including the transmitter non-idealities, sensitivities at 20 Gb/s and 30 Gb/s of-8.2 dBni and -7.5 dBm, respectively, at a BER = 10-12 were measured. The complete receiver consumes 56 mW from a 1.1-V supply and occupies a chip area of 230 mum x 220 mum only.