{"title":"A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward Compensations","authors":"M. Shen, Li-Han Hung, Po-Chiun Huang","doi":"10.1109/ASSCC.2006.357878","DOIUrl":null,"url":null,"abstract":"This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-mum CMOS technology, measurement results demonstrate that DC gain greater than 90 dB, gain-bandwidth product of 8.9 MHz, and phase margin of 86deg is achieved with lOOpF output loads. The settling time for a 1.2 Vpp step is 2.4 mus. All the circuits dissipate 342 muW under a single 1.2V power supply.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"243 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357878","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-mum CMOS technology, measurement results demonstrate that DC gain greater than 90 dB, gain-bandwidth product of 8.9 MHz, and phase margin of 86deg is achieved with lOOpF output loads. The settling time for a 1.2 Vpp step is 2.4 mus. All the circuits dissipate 342 muW under a single 1.2V power supply.
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