Cognitive Bus Coding Scheme for Inter-Chip Communications of Deep Learning Accelerator Chiplet on Low-cost Si and Glass Interposer

Abstract

In the present Artificial Intelligence (AI) hardware research, interposer based multi-chip Deep Learning Accelerator (DLA) system is one of the main technology. Silicon (Si) interposer is the main key in the emerging 2.5D integration process. However, signal integrity is limited by the capacitive crosstalk and signal reflection can lead to notch attack in some frequency bands. In this paper, two new bus coding schemes are proposed to improve signal integrity, reducing the crosstalk to increase bandwidth for on-silicon-interposer and on-glass-interposer inter-chip data communications. For silicon interposer, a joint code division multiple access and crosstalk avoidance coding (Joint CDMA/CAC) scheme is proposed to reduce the capacitive crosstalk effect for fine-pitch interconnects. The eye diagram and bit error rate are both improved, and the average crosstalk effect is reduced by half. Also, a cognitive bus coding scheme is proposed by spread spectrum and channel learning for glass interposer. The proposed cognitive bus coding increases the total data bandwidth under frequency notches based on the channel condition for modulation.