An on-chip calibration technique for reducing temperature and offset errors in a programmable voltage reference

Abstract

We present an on-chip calibration method for reducing offset errors and variations of the temperature coefficient of the output voltage of a programmable voltage reference. The offset calibration can be performed by an automatic on-chip calibration procedure or by directly programming an appropriate calibration value via a Three-Wire-Interface. Variation of the temperature coefficients can be compensated by taking into account the measured output voltage at two arbitrary temperatures during e.g. wafer sort and final test, and setting a corresponding calibration value. Extensive simulations and measurements indicate that the error due to variations in temperature coefficients can be reduced by 40% and the overall offset error can be improved up to 90% of the uncalibrated voltage reference.