Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188948
A. Castro-Carranza, J. Nolasco, M. Estrada, Y. Xu, M. Benwadih, R. Gwoziecki, A. Cerdeira, G. Ghibaudo, B. Iñiguez, J. Pallarès
In this paper we show that the mobility reduces for OTFTs with similar channel length when the channel width is increased. The effect is shown in staggered bottom contact organic thin film transitors (OTFTs) made of the P-Type semiconductor Poly(Triarylamine) PTAA and Cytop® as insulator. It can also be seen from experiment, that this mobility reduction is associated to an increase in the density of localized traps present in the active layer material. An interpretation of this effect is presented.
{"title":"Study of the interface area effect on the density of states in PTAA-Cytop® OTFTs","authors":"A. Castro-Carranza, J. Nolasco, M. Estrada, Y. Xu, M. Benwadih, R. Gwoziecki, A. Cerdeira, G. Ghibaudo, B. Iñiguez, J. Pallarès","doi":"10.1109/ICCDCS.2012.6188948","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188948","url":null,"abstract":"In this paper we show that the mobility reduces for OTFTs with similar channel length when the channel width is increased. The effect is shown in staggered bottom contact organic thin film transitors (OTFTs) made of the P-Type semiconductor Poly(Triarylamine) PTAA and Cytop® as insulator. It can also be seen from experiment, that this mobility reduction is associated to an increase in the density of localized traps present in the active layer material. An interpretation of this effect is presented.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117135758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188894
D. Gruber, T. Ostermann
We present an on-chip calibration method for reducing offset errors and variations of the temperature coefficient of the output voltage of a programmable voltage reference. The offset calibration can be performed by an automatic on-chip calibration procedure or by directly programming an appropriate calibration value via a Three-Wire-Interface. Variation of the temperature coefficients can be compensated by taking into account the measured output voltage at two arbitrary temperatures during e.g. wafer sort and final test, and setting a corresponding calibration value. Extensive simulations and measurements indicate that the error due to variations in temperature coefficients can be reduced by 40% and the overall offset error can be improved up to 90% of the uncalibrated voltage reference.
{"title":"An on-chip calibration technique for reducing temperature and offset errors in a programmable voltage reference","authors":"D. Gruber, T. Ostermann","doi":"10.1109/ICCDCS.2012.6188894","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188894","url":null,"abstract":"We present an on-chip calibration method for reducing offset errors and variations of the temperature coefficient of the output voltage of a programmable voltage reference. The offset calibration can be performed by an automatic on-chip calibration procedure or by directly programming an appropriate calibration value via a Three-Wire-Interface. Variation of the temperature coefficients can be compensated by taking into account the measured output voltage at two arbitrary temperatures during e.g. wafer sort and final test, and setting a corresponding calibration value. Extensive simulations and measurements indicate that the error due to variations in temperature coefficients can be reduced by 40% and the overall offset error can be improved up to 90% of the uncalibrated voltage reference.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121044160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188940
A. Ximenes, J. Swart
This paper presents the design and analysis of a Mixer in 0.13-μm RFCMOS process for Direct-Conversion Receivers (DCRs), with RF input frequency ranging from 50 MHz up to 6.5 GHz. This circuit has been designed to provide an intermediate input impedance, being suitable for either direct antenna connection or integrated with a LNA. This mixer attends the necessary requirements of a cognitive radio (CR), including wideband operation along with good linearity. It is based on a Gilbert-cell using the current bleeding technique with two series resonating inductors. It has a measured conversion gain of 16 dB, a measured input third-order intercept point of -1 dBm, a simulated noise figure of 8.5 dB at 1 MHz, while consuming only 4.5 mW of dc power.
{"title":"A CMOS wideband mixer for Direct-Conversion Receivers (DCRs)","authors":"A. Ximenes, J. Swart","doi":"10.1109/ICCDCS.2012.6188940","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188940","url":null,"abstract":"This paper presents the design and analysis of a Mixer in 0.13-μm RFCMOS process for Direct-Conversion Receivers (DCRs), with RF input frequency ranging from 50 MHz up to 6.5 GHz. This circuit has been designed to provide an intermediate input impedance, being suitable for either direct antenna connection or integrated with a LNA. This mixer attends the necessary requirements of a cognitive radio (CR), including wideband operation along with good linearity. It is based on a Gilbert-cell using the current bleeding technique with two series resonating inductors. It has a measured conversion gain of 16 dB, a measured input third-order intercept point of -1 dBm, a simulated noise figure of 8.5 dB at 1 MHz, while consuming only 4.5 mW of dc power.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115198586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188947
O. Koudriavtseva, Y. Kudriavtsev, A. Escobosa, V. M. Sanchez-R
An irregular erosion rate in SIMS can lead to erroneous results during depth profiling analysis of semiconductor hetero-structures. In this work the dependence of erosion on the composition of AlxGA1-xAs is determined. High resolution X-ray diffraction is used to measure the alloy composition considering the deformation due to a good coupling between substrate and layer. The result shows that the erosion rate is reduced to 70% when the AlAs fraction (x) increases from 0 to 0.65.
{"title":"Determination of the ion erosion rate during the SIMS analysis on AlxGa1−xAs as a function of x using HRXRD","authors":"O. Koudriavtseva, Y. Kudriavtsev, A. Escobosa, V. M. Sanchez-R","doi":"10.1109/ICCDCS.2012.6188947","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188947","url":null,"abstract":"An irregular erosion rate in SIMS can lead to erroneous results during depth profiling analysis of semiconductor hetero-structures. In this work the dependence of erosion on the composition of AlxGA1-xAs is determined. High resolution X-ray diffraction is used to measure the alloy composition considering the deformation due to a good coupling between substrate and layer. The result shows that the erosion rate is reduced to 70% when the AlAs fraction (x) increases from 0 to 0.65.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"297 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116254016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188900
R. K. Sharma, A. Antonopoulos, N. Mavredakis, M. Bucher
Analog/RF performance of gate stack dual material double gate (GSDMDG) and graded channel gate stack double gate (GCGSDG) has been examined by ATLAS device simulation, including quantum confinement. We propose two new analog/RF figures of merit, 1) gain frequency product (GFP) which combines both low- and high-frequency aspects of device operation, 2) gain transconductance frequency product (GTFP) that includes both the switching speed and intrinsic gain of the device and is very useful for circuit design. The GCGSDG shows higher transconductance frequency product (TFP) and is a good candidate for high speed switching applications. However, GSDMDG outperforms other devices in terms of GTFP.
{"title":"Analog/RF figures of merit of advanced DG MOSFETs","authors":"R. K. Sharma, A. Antonopoulos, N. Mavredakis, M. Bucher","doi":"10.1109/ICCDCS.2012.6188900","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188900","url":null,"abstract":"Analog/RF performance of gate stack dual material double gate (GSDMDG) and graded channel gate stack double gate (GCGSDG) has been examined by ATLAS device simulation, including quantum confinement. We propose two new analog/RF figures of merit, 1) gain frequency product (GFP) which combines both low- and high-frequency aspects of device operation, 2) gain transconductance frequency product (GTFP) that includes both the switching speed and intrinsic gain of the device and is very useful for circuit design. The GCGSDG shows higher transconductance frequency product (TFP) and is a good candidate for high speed switching applications. However, GSDMDG outperforms other devices in terms of GTFP.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"350 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125630258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188881
S. Saberhosseini, A. Zabihian, A. M. Sodagar
This paper presents an ultra low-power operational transconductance amplifier (OTA), which can be used in the implementation of preconditioning stage of implantable neural recording microsystems. In such applications, low-noise performance is both critical and challenging especially at very low power consumptions. By means of a new structure for OTA, a low-noise, low-power, and small-silicon-area OTA is proposed. The OTA was designed in a 0.5-μm standard 2P3M N-Well CMOS process. Simulation results for the proposed OTA show an open-loop gain of 62dB, unity-gain bandwidth of 4MHz, and 59nVrms/√Hz input-referred noise. Power dissipation of the OTA is as low as 4μW at 3-V supply voltage.
{"title":"Low-noise OTA for neural amplifying applications","authors":"S. Saberhosseini, A. Zabihian, A. M. Sodagar","doi":"10.1109/ICCDCS.2012.6188881","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188881","url":null,"abstract":"This paper presents an ultra low-power operational transconductance amplifier (OTA), which can be used in the implementation of preconditioning stage of implantable neural recording microsystems. In such applications, low-noise performance is both critical and challenging especially at very low power consumptions. By means of a new structure for OTA, a low-noise, low-power, and small-silicon-area OTA is proposed. The OTA was designed in a 0.5-μm standard 2P3M N-Well CMOS process. Simulation results for the proposed OTA show an open-loop gain of 62dB, unity-gain bandwidth of 4MHz, and 59nVrms/√Hz input-referred noise. Power dissipation of the OTA is as low as 4μW at 3-V supply voltage.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133778359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188895
A. Cerdeira, M. Estrada, R. Ritzenthaler, J. Franco, M. Togo, C. Claeys
Multiple-gate MOSFETs are widely recognized as the most promising nanometric transistors for end of roadmap integrated circuits. These devices have therefore a great potential for low voltage, low power analog and digital applications. FinFETs fabricated on bulk wafers gained attention due to the possibility of their integration with standard bulk CMOS technology and reduced wafer cost. In the present work, the charge based Symmetric Doped Double-Gate Model (SDDGM) is applied to this new generation of FinFETs transistors, showing the possibilities of this model to describe the transistor behavior in all operating regions and at different temperatures. Three types of bulk FinFETS were modeled, including N-type and P-type. Comparison between measured and modeled transfer characteristics in all regions of operation, and varying the operating temperature from 25°C to 175°C, gives a good agreement extracting only eight parameters. These results demonstrated that the model SDDGM is also suitable for using in circuit simulation of chips bulk FinFETs devices.
{"title":"Charge based compact model for bulk FinFETs","authors":"A. Cerdeira, M. Estrada, R. Ritzenthaler, J. Franco, M. Togo, C. Claeys","doi":"10.1109/ICCDCS.2012.6188895","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188895","url":null,"abstract":"Multiple-gate MOSFETs are widely recognized as the most promising nanometric transistors for end of roadmap integrated circuits. These devices have therefore a great potential for low voltage, low power analog and digital applications. FinFETs fabricated on bulk wafers gained attention due to the possibility of their integration with standard bulk CMOS technology and reduced wafer cost. In the present work, the charge based Symmetric Doped Double-Gate Model (SDDGM) is applied to this new generation of FinFETs transistors, showing the possibilities of this model to describe the transistor behavior in all operating regions and at different temperatures. Three types of bulk FinFETS were modeled, including N-type and P-type. Comparison between measured and modeled transfer characteristics in all regions of operation, and varying the operating temperature from 25°C to 175°C, gives a good agreement extracting only eight parameters. These results demonstrated that the model SDDGM is also suitable for using in circuit simulation of chips bulk FinFETs devices.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115532981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188941
C. Soria-Lopez, R. M. Ramos
Jitter, delay, and packet loss are the main factors impacting voice quality of interactive VoIP sessions on today's Internet. Such phenomena are often amplified when operating over mobile ad hoc networks (MANETs), so providing VoIP services over this kind of networks represents a huge challenge. On one hand, the routing protocol used by a MANET plays a very important role on the performance of VoIP sessions. On the other hand, playout delay control algorithms play another crucial role on VoIP, and are helpful to smooth the effects of jitter and to improve the interactivity of VoIP sessions. Such playout delay control algorithms trade-off the time that voice packets spend in the receiver's buffer while keeping an acceptable packet loss rate. In this paper, we evaluate the performance of playout delay control algorithms for VoIP over MANETs by testing algorithms that are already widely accepted and stable on the Internet.
{"title":"Applying traditional VoIP playout delay control algorithms to MANETs","authors":"C. Soria-Lopez, R. M. Ramos","doi":"10.1109/ICCDCS.2012.6188941","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188941","url":null,"abstract":"Jitter, delay, and packet loss are the main factors impacting voice quality of interactive VoIP sessions on today's Internet. Such phenomena are often amplified when operating over mobile ad hoc networks (MANETs), so providing VoIP services over this kind of networks represents a huge challenge. On one hand, the routing protocol used by a MANET plays a very important role on the performance of VoIP sessions. On the other hand, playout delay control algorithms play another crucial role on VoIP, and are helpful to smooth the effects of jitter and to improve the interactivity of VoIP sessions. Such playout delay control algorithms trade-off the time that voice packets spend in the receiver's buffer while keeping an acceptable packet loss rate. In this paper, we evaluate the performance of playout delay control algorithms for VoIP over MANETs by testing algorithms that are already widely accepted and stable on the Internet.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116031997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188921
Zhuochao Sun, C. Jin, L. Siek
Driven by the battery-operated applications in portable devices, circuit design techniques for reducing the power consumption have been extensively investigated in the past decade. One common approach is the supply voltage scaling, where different voltages are generated by DC-DC converters and provided to corresponding low supply circuits. Because each circuit is supplied by the lowest possible voltage, the power consumption is greatly reduced. However, the voltage converters employed in this method bring in extra design cost and power consumption. Therefore in this paper, the voltage converter is removed from conventional design and the possibility of stacking multiple low supply circuits to achieve virtual supply voltage scaling is discussed. The proposed technique connects the stacking circuits directly to the high voltage source. It saves one or more voltage converters, therefore reduces the chip area and eliminates the power loss associated with the converters. The proposed stacking structure is more applicable to systems with single high voltage supply.
{"title":"Low power integrated circuit design with stacking technique","authors":"Zhuochao Sun, C. Jin, L. Siek","doi":"10.1109/ICCDCS.2012.6188921","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188921","url":null,"abstract":"Driven by the battery-operated applications in portable devices, circuit design techniques for reducing the power consumption have been extensively investigated in the past decade. One common approach is the supply voltage scaling, where different voltages are generated by DC-DC converters and provided to corresponding low supply circuits. Because each circuit is supplied by the lowest possible voltage, the power consumption is greatly reduced. However, the voltage converters employed in this method bring in extra design cost and power consumption. Therefore in this paper, the voltage converter is removed from conventional design and the possibility of stacking multiple low supply circuits to achieve virtual supply voltage scaling is discussed. The proposed technique connects the stacking circuits directly to the high voltage source. It saves one or more voltage converters, therefore reduces the chip area and eliminates the power loss associated with the converters. The proposed stacking structure is more applicable to systems with single high voltage supply.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"46 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124667138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-14DOI: 10.1109/ICCDCS.2012.6188936
J. Alvarado, J. Tinoco, V. Kilchytska, D. Flandre, J. Raskin, A. Cerdeira, E. Contreras
Modeling of the small-signal equivalent circuit of SOI FinFETs through SPICE simulations is presented. A compact model implemented in Verilog-A predicts well the DC characteristics of RF SOI FinFETs and allows the extraction of the intrinsic conductance, transconductance and capacitances at any selected operating point. The intrinsic small-signal equivalent circuit composed of those extracted lumped elements is used in SPICE simulator. This paper compares the parameters extracted from both DC and wideband S-parameter methods.
通过SPICE仿真对SOI finfet的小信号等效电路进行了建模。在Verilog-A中实现的紧凑模型很好地预测了RF SOI finfet的直流特性，并允许提取任何选定工作点的固有电导，跨电导和电容。将这些提取的集总元件组成的本征小信号等效电路用于SPICE模拟器。本文比较了直流法和宽带s参数法提取的参数。
{"title":"Compact small-signal model for RF FinFETs","authors":"J. Alvarado, J. Tinoco, V. Kilchytska, D. Flandre, J. Raskin, A. Cerdeira, E. Contreras","doi":"10.1109/ICCDCS.2012.6188936","DOIUrl":"https://doi.org/10.1109/ICCDCS.2012.6188936","url":null,"abstract":"Modeling of the small-signal equivalent circuit of SOI FinFETs through SPICE simulations is presented. A compact model implemented in Verilog-A predicts well the DC characteristics of RF SOI FinFETs and allows the extraction of the intrinsic conductance, transconductance and capacitances at any selected operating point. The intrinsic small-signal equivalent circuit composed of those extracted lumped elements is used in SPICE simulator. This paper compares the parameters extracted from both DC and wideband S-parameter methods.","PeriodicalId":125743,"journal":{"name":"2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128953777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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