The cycle accurate DSP model design based on SystemC

Lin Dai, Zhenyao Liu
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Abstract

With the development of the DSP design technique, the DSP structure becomes more and more complex and the speed of RTL simulation is slower and slower. In this paper, a cycle accurate DSP model based on SystemC is designed to speed up the simulation. Through the simulation of g.721 audio encoding program and the IDCT that is the main part of image processing, the time of cycle accurate DSP model simulation is about one minute and ten seconds, however the time of RTL simulation is about thirty minutes and five minutes.
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基于SystemC的周期精确DSP模型设计
随着DSP设计技术的发展,DSP结构越来越复杂,RTL仿真速度越来越慢。为了加快仿真速度,本文设计了基于SystemC的周期精确DSP模型。通过对g.721音频编码程序和图像处理主要部分IDCT的仿真,周期精确DSP模型仿真时间约为1分10秒,而RTL仿真时间约为30分5分钟。
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