A Novel Low-power Neuromorphic Circuit based on Izhikevich Model

Maria Sapounaki, A. Kakarountas
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Abstract

In recent years, scientists strove to create devices that may ameliorate patients’ lives who suffer from a neuronal disease. These devices are mainly based on neuromorphic circuits and usually employ mathematical equations. This paper implements Izhikevich (IZH) mathematical model on an FPGA board. The paper proposes an innovative hardware architecture that creates an application-specific Processing Unit for implementing a neuron. The design achieves to decrease power consumption by 37,5% and 16% of the dynamic and the total power consumption, respectively, while maintaining the computational speed at the same level, compared to similar works.
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一种基于Izhikevich模型的新型低功耗神经形态电路
近年来,科学家们努力创造出可以改善患有神经疾病的患者生活的设备。这些装置主要基于神经形态回路,通常采用数学方程式。本文在FPGA板上实现了Izhikevich (IZH)数学模型。本文提出了一种创新的硬件架构,它创建了一个特定于应用程序的处理单元来实现神经元。与同类产品相比,在保持计算速度不变的情况下,实现了动态功耗和总功耗分别降低37.5%和16%。
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