An Area Efficient Diode and On Transistor Interchangeable Power Gating Scheme with Trim Options for Low Power SRAMs

Abstract

Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells through diode transistor in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, the source voltage cannot be raised beyond a certain level. To achieve that, the size of the required diode transistor becomes larger, as the supply voltage shrinks in the nano-CMOS technologies. In this work, an area efficient power gating technique with capability of post-silicon trimming of the voltage across SRAM cell is presented. Proposed interchangeable on transistor and diode scheme reduces the area overhead by 40% compared to conventional schemes, when applied to a 16Kb SRAM macro at 28nm CMOS technology at 0.85V supply voltage. Trimmable power gating scheme provides many options to trim the SRAM source voltage (ranging from 50mV to 150 mV in steps of approx. 25mV) with approx. 3% area overhead and more flexibility over conventional schemes.