Ryuichi Nakajima, Kazuya Ioki, J. Furuta, Kazutoshi Kobayashi
{"title":"Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process","authors":"Ryuichi Nakajima, Kazuya Ioki, J. Furuta, Kazutoshi Kobayashi","doi":"10.1109/IOLTS56730.2022.9897814","DOIUrl":null,"url":null,"abstract":"We examined the radiation hardness of the several types of flip-flops fabricated in a 130 nm bulk process by alpha-ray irradiation tests and circuit simulation. The simulated $\\alpha -$SER of FFs with the critical charge larger than 14 fC becomes 1/100 of that with the critical charge of 10 fC. We propose a radiation-hardened flip-flop minimizing area, delay, and power overheads with 1/100 lower $\\alpha -$SER in a 130 nm bulk process. The radiation hardness is achieved by adding series transistors and wires with only less than 14% area, 7% delay, and 12% power overheads in order to increase the critical charge. Alpha-ray irradiation tests revealed that the proposed method can reduce soft error rates to 1/100.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IOLTS56730.2022.9897814","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We examined the radiation hardness of the several types of flip-flops fabricated in a 130 nm bulk process by alpha-ray irradiation tests and circuit simulation. The simulated $\alpha -$SER of FFs with the critical charge larger than 14 fC becomes 1/100 of that with the critical charge of 10 fC. We propose a radiation-hardened flip-flop minimizing area, delay, and power overheads with 1/100 lower $\alpha -$SER in a 130 nm bulk process. The radiation hardness is achieved by adding series transistors and wires with only less than 14% area, 7% delay, and 12% power overheads in order to increase the critical charge. Alpha-ray irradiation tests revealed that the proposed method can reduce soft error rates to 1/100.