Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897477
Kota Hisafuru, Kazunari Takasaki, N. Togawa
In recent years, with the wide spread of the Internet of Things (IoT) devices, security issues for hardware devices have been increasing, where detecting their anomalous behaviors becomes quite important. One of the effective methods for detecting anomalous behaviors of IoT devices is to utilize operation duration time and consumed energy extracted from their power waveforms. However, the existing methods do not consider the shape of time-series data and cannot distinguish between power waveforms with similar duration time and consumed energy but different shapes. In this paper, we propose a method for detecting anomalous behaviors based on the shape of time-series data by incorporating a shape-based distance (SBD) measure. The proposed method firstly obtains the entire power waveform of the target IoT device and extract several application power waveforms. After that, we give the invariances to them and we can effectively obtain the SBD between every two application power waveforms. Based on the SBD values, the local outlier factor (LOF) method can finally distinguish between normal application behaviors and anomalous application behaviors. Experimental results demonstrate that the proposed method successfully detects the anomalous application behaviors, while the existing method fails to detect them.
{"title":"An Anomalous Behavior Detection Method for IoT Devices Based on Power Waveform Shapes","authors":"Kota Hisafuru, Kazunari Takasaki, N. Togawa","doi":"10.1109/IOLTS56730.2022.9897477","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897477","url":null,"abstract":"In recent years, with the wide spread of the Internet of Things (IoT) devices, security issues for hardware devices have been increasing, where detecting their anomalous behaviors becomes quite important. One of the effective methods for detecting anomalous behaviors of IoT devices is to utilize operation duration time and consumed energy extracted from their power waveforms. However, the existing methods do not consider the shape of time-series data and cannot distinguish between power waveforms with similar duration time and consumed energy but different shapes. In this paper, we propose a method for detecting anomalous behaviors based on the shape of time-series data by incorporating a shape-based distance (SBD) measure. The proposed method firstly obtains the entire power waveform of the target IoT device and extract several application power waveforms. After that, we give the invariances to them and we can effectively obtain the SBD between every two application power waveforms. Based on the SBD values, the local outlier factor (LOF) method can finally distinguish between normal application behaviors and anomalous application behaviors. Experimental results demonstrate that the proposed method successfully detects the anomalous application behaviors, while the existing method fails to detect them.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127538121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897769
N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero
In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of $F_{max}$, that is, the maximum operating frequency. It has been demonstrated that data extracted from on-chip speed monitors can model the $F_{max}$ of integrated circuits by means of machine learning models, and that those models are suitable for the performance screening process. However, while acquiring data from these monitors is quite an accurate process, the labelling is time-consuming, costly, and may be subject to different measurements errors, impairing the final quality. This paper presents a methodology to cope with anomalous and noisy data in the context of the multi-label regression problem of microcontroller performance screening. We used outlier detection based on Inter Quartile Range (IQR) and Z-score and imputation techniques to detect errors in the labels and to avoid to drop incomplete samples, building higher-quality training set for our models, optimizing the devices characterization phase. Experiments showed that the proposed methodology increases the performance of existing models, making them more robust. These techniques permitted us to use a significantly smaller number of samples (about one third of the devices available for characterization), thus making the costly data acquisition process more efficient.
{"title":"Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data","authors":"N. Bellarmino, R. Cantoro, M. Huch, T. Kilian, Ulf Schlichtmann, Giovanni Squillero","doi":"10.1109/IOLTS56730.2022.9897769","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897769","url":null,"abstract":"In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of $F_{max}$, that is, the maximum operating frequency. It has been demonstrated that data extracted from on-chip speed monitors can model the $F_{max}$ of integrated circuits by means of machine learning models, and that those models are suitable for the performance screening process. However, while acquiring data from these monitors is quite an accurate process, the labelling is time-consuming, costly, and may be subject to different measurements errors, impairing the final quality. This paper presents a methodology to cope with anomalous and noisy data in the context of the multi-label regression problem of microcontroller performance screening. We used outlier detection based on Inter Quartile Range (IQR) and Z-score and imputation techniques to detect errors in the labels and to avoid to drop incomplete samples, building higher-quality training set for our models, optimizing the devices characterization phase. Experiments showed that the proposed methodology increases the performance of existing models, making them more robust. These techniques permitted us to use a significantly smaller number of samples (about one third of the devices available for characterization), thus making the costly data acquisition process more efficient.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122947750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897537
A. Kritikakou, Panagiota Nikolaou, Ivan Rodriguez-Ferrandez, Joseph Paturel, Leonidas Kosmidis, M. Michael, O. Sentieys, D. Steenari
Embedded systems in critical domains, such as auto-motive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implemented at various levels of the system design, in order to maintain the functional correctness. However, transient faults and their mitigation methods have a timing impact, which can affect the temporal correctness of the system. In this work, we expose the functional and the timing implications of transient faults for critical systems. More precisely, we initially highlight the timing effect of transient faults occurring in the combinational and sequential logic of a processor. Furthermore, we propose a full stack vulnerability analysis that drives the design of selective hardware-based mitigation for real-time applications. Last, we study the timing impact of software-based reliability mitigation methods applied in a COTS GPU, using a fault tolerant middleware.
{"title":"Functional and Timing Implications of Transient Faults in Critical Systems","authors":"A. Kritikakou, Panagiota Nikolaou, Ivan Rodriguez-Ferrandez, Joseph Paturel, Leonidas Kosmidis, M. Michael, O. Sentieys, D. Steenari","doi":"10.1109/IOLTS56730.2022.9897537","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897537","url":null,"abstract":"Embedded systems in critical domains, such as auto-motive, aviation, space domains, are often required to guarantee both functional and temporal correctness. Considering transient faults, fault analysis and mitigation approaches are implemented at various levels of the system design, in order to maintain the functional correctness. However, transient faults and their mitigation methods have a timing impact, which can affect the temporal correctness of the system. In this work, we expose the functional and the timing implications of transient faults for critical systems. More precisely, we initially highlight the timing effect of transient faults occurring in the combinational and sequential logic of a processor. Furthermore, we propose a full stack vulnerability analysis that drives the design of selective hardware-based mitigation for real-time applications. Last, we study the timing impact of software-based reliability mitigation methods applied in a COTS GPU, using a fault tolerant middleware.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114836881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897284
G. Duchrau, M. Gössel
In this paper a new and simple method for 2-bit error correction for cross parity codes is proposed. All single and double bit errors, concerning data bits, are corrected. For checkbit errors up to a weight of 2, this method ensures that the data bits are free of errors. In a cross parity code the data bits are conceptually arranged in a rectangular array. The check sums are formed over bits along columns, rows and diagonals. In addition, the parity of all data bits is determined. If a 1-bit error occurs in the data bits, the erroneous bit is located at the intersection of three straight lines: a row, a column and a diagonal. For 2-bit data errors on distinct lines, the erroneous bits are located in the same way. For 2-bit data errors, that share a line, two straight lines per erroneous bit can be identified by the check bits. In a first step the bits at the four intersection points are inverted. Thereby the two errors are corrected and two new errors are generated. In case of odd side length, the two generated errors are located at three different straight lines each and can be easily corrected in a second step.
{"title":"A New Decoding Method for Double Error Correcting Cross Parity Codes","authors":"G. Duchrau, M. Gössel","doi":"10.1109/IOLTS56730.2022.9897284","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897284","url":null,"abstract":"In this paper a new and simple method for 2-bit error correction for cross parity codes is proposed. All single and double bit errors, concerning data bits, are corrected. For checkbit errors up to a weight of 2, this method ensures that the data bits are free of errors. In a cross parity code the data bits are conceptually arranged in a rectangular array. The check sums are formed over bits along columns, rows and diagonals. In addition, the parity of all data bits is determined. If a 1-bit error occurs in the data bits, the erroneous bit is located at the intersection of three straight lines: a row, a column and a diagonal. For 2-bit data errors on distinct lines, the erroneous bits are located in the same way. For 2-bit data errors, that share a line, two straight lines per erroneous bit can be identified by the check bits. In a first step the bits at the four intersection points are inverted. Thereby the two errors are corrected and two new errors are generated. In case of odd side length, the two generated errors are located at three different straight lines each and can be easily corrected in a second step.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133103331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897183
Anu Bala, S. Khandelwal, A. Jabir, M. Ottavi
This paper evaluates the yield of a memristor-based crossbar array of artificial neural networks in the presence of stuck-at-faults (SAFs). A technique based on Markov chains is used to estimate the yield in the presence of stuck-at-faults. This method provides a high degree of accuracy. Another method that is used for analysis and comparison is the Poisson distribution, which uses the sum of all repairable fault patterns. A fault repair mechanism is also considered when evaluating the yield of the memristor crossbar array. The results demonstrate that the yield could be improved with redundancies and a higher repairable stuck-at-fault ratio.
{"title":"Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability","authors":"Anu Bala, S. Khandelwal, A. Jabir, M. Ottavi","doi":"10.1109/IOLTS56730.2022.9897183","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897183","url":null,"abstract":"This paper evaluates the yield of a memristor-based crossbar array of artificial neural networks in the presence of stuck-at-faults (SAFs). A technique based on Markov chains is used to estimate the yield in the presence of stuck-at-faults. This method provides a high degree of accuracy. Another method that is used for analysis and comparison is the Poisson distribution, which uses the sum of all repairable fault patterns. A fault repair mechanism is also considered when evaluating the yield of the memristor crossbar array. The results demonstrate that the yield could be improved with redundancies and a higher repairable stuck-at-fault ratio.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115565242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897425
Christos Zonios, V. Tenentes
Software and hardware vulnerabilities to power side-channel attacks (SCA) are hard to detect and mitigate in systems already deployed in-the-field, because they require specialized equipment and aligned power traces. In this paper, we present REVOLVER, a software-based framework that performs zero-step execution emulation and generates power traces with instruction-level resolution. REVOLVER is a hybrid emulator, because part of it runs on the system that it emulates, an actual ARM64 platform, and evaluates the power consumption of its emulated instructions using actual measurements from on-chip low-frequency power sensors. Such sensors are already present on many system-on-chips (SoCs). To improve the accuracy of the collected traces, REVOLVER repeats the execution of the instructions in a zero-step fashion. To demonstrate the capabilities of our framework, we show that AES keys can be recovered by Correlation Power Analysis (CPA) on traces acquired using REVOLVER, which proves experimentally that there is a leaking power side-channel in the examined system that could potentially be exploited by power SCAs. Moreover, we show how REVOLVER can be used by a security engineer not only to identify software and hardware vulnerabilities to power SCAs, but also to design and evaluate mitigation strategies.
{"title":"REVOLVER: A Zero-Step Execution Emulation Framework for Mitigating Power Side-Channel Attacks on ARM64","authors":"Christos Zonios, V. Tenentes","doi":"10.1109/IOLTS56730.2022.9897425","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897425","url":null,"abstract":"Software and hardware vulnerabilities to power side-channel attacks (SCA) are hard to detect and mitigate in systems already deployed in-the-field, because they require specialized equipment and aligned power traces. In this paper, we present REVOLVER, a software-based framework that performs zero-step execution emulation and generates power traces with instruction-level resolution. REVOLVER is a hybrid emulator, because part of it runs on the system that it emulates, an actual ARM64 platform, and evaluates the power consumption of its emulated instructions using actual measurements from on-chip low-frequency power sensors. Such sensors are already present on many system-on-chips (SoCs). To improve the accuracy of the collected traces, REVOLVER repeats the execution of the instructions in a zero-step fashion. To demonstrate the capabilities of our framework, we show that AES keys can be recovered by Correlation Power Analysis (CPA) on traces acquired using REVOLVER, which proves experimentally that there is a leaking power side-channel in the examined system that could potentially be exploited by power SCAs. Moreover, we show how REVOLVER can be used by a security engineer not only to identify software and hardware vulnerabilities to power SCAs, but also to design and evaluate mitigation strategies.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125971496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897189
W. Cruz, R. Viera, J. Rigaud, G. Hubert, J. Dutertre
This work reports LFI experiments carried out on custom CMOS 65 nm digital test gates, aiming at tuning the parameters of a compact electrical model. Like in previous works, we observed a difference in behavior in the induced faults when using nanosecond and picosecond range laser pulse duration. However, our experimental results showed that the laser-sensitive areas were restricted to the PMOS transistors for ns laser pulses, contrary to what was previously stated in the literature. For ps pulse duration, these works outline the sensitivity of both the NMOS and PMOS of an SRAM cell following the theoretical model of LFI. These experiments help to calibrate the parameters of a compact electrical model, allowing the simulation of LFI attacks (using SPICE-like CAD tools). This compact model is built upon previous works, with simplifications to facilitate its use. Once tuned, simulations using the proposed compact model exhibit a good correlation with the experimental results.
{"title":"An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation","authors":"W. Cruz, R. Viera, J. Rigaud, G. Hubert, J. Dutertre","doi":"10.1109/IOLTS56730.2022.9897189","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897189","url":null,"abstract":"This work reports LFI experiments carried out on custom CMOS 65 nm digital test gates, aiming at tuning the parameters of a compact electrical model. Like in previous works, we observed a difference in behavior in the induced faults when using nanosecond and picosecond range laser pulse duration. However, our experimental results showed that the laser-sensitive areas were restricted to the PMOS transistors for ns laser pulses, contrary to what was previously stated in the literature. For ps pulse duration, these works outline the sensitivity of both the NMOS and PMOS of an SRAM cell following the theoretical model of LFI. These experiments help to calibrate the parameters of a compact electrical model, allowing the simulation of LFI attacks (using SPICE-like CAD tools). This compact model is built upon previous works, with simplifications to facilitate its use. Once tuned, simulations using the proposed compact model exhibit a good correlation with the experimental results.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125027491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897647
P. Bernardi, R. Cantoro, Anthony Coyette, W. Dobbeleare, M. Fieback, A. Floridia, G. Gielenk, Jhon Gomez, M. Grosso, Andrea Guerriero, I. Guglielminetti, S. Hamdioui, Giorgio Insinga, N. Mautone, Nunzio Mirabella, Sandro Sartoni, M. Reorda, R. Ullmann, Ronny Vanhooren, N. Xamak, Lizhou Wu
Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips utilized in mission-critical applications. The research community and industry have been investigating new test approaches such as device-aware test, cell-aware test, path-delay test, and even test methodologies based on the analysis of manufacturing data to move the scope from OPPM to OPPB. This special session presents four contributions, from academic researchers and industry professionals, to enable better chip quality. We present results on various activities towards this objective, including device-aware test, software-based self-test, and memory test.
{"title":"Recent Trends and Perspectives on Defect-Oriented Testing","authors":"P. Bernardi, R. Cantoro, Anthony Coyette, W. Dobbeleare, M. Fieback, A. Floridia, G. Gielenk, Jhon Gomez, M. Grosso, Andrea Guerriero, I. Guglielminetti, S. Hamdioui, Giorgio Insinga, N. Mautone, Nunzio Mirabella, Sandro Sartoni, M. Reorda, R. Ullmann, Ronny Vanhooren, N. Xamak, Lizhou Wu","doi":"10.1109/IOLTS56730.2022.9897647","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897647","url":null,"abstract":"Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips utilized in mission-critical applications. The research community and industry have been investigating new test approaches such as device-aware test, cell-aware test, path-delay test, and even test methodologies based on the analysis of manufacturing data to move the scope from OPPM to OPPB. This special session presents four contributions, from academic researchers and industry professionals, to enable better chip quality. We present results on various activities towards this objective, including device-aware test, software-based self-test, and memory test.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128458038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897452
Giovanni Corrente, N. Bentivegna, S. Russo
The aim of this paper is to analyze the planar SiC MOSFETs behavior under power cycle current flow on body diode. In particular, the activity highlights how this type of trials, in addition to stimulate failure mechanisms directly related to metal fatigue, is able to stimulate failure mechanisms that seem not directly related to metal fatigue. The activity was developed by supporting the analysis of data obtained through laboratory measurements from a careful study of Failure Analysis (FA).
{"title":"Power Cycling Body Diode Current Flow on SiC MOSFET Device","authors":"Giovanni Corrente, N. Bentivegna, S. Russo","doi":"10.1109/IOLTS56730.2022.9897452","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897452","url":null,"abstract":"The aim of this paper is to analyze the planar SiC MOSFETs behavior under power cycle current flow on body diode. In particular, the activity highlights how this type of trials, in addition to stimulate failure mechanisms directly related to metal fatigue, is able to stimulate failure mechanisms that seem not directly related to metal fatigue. The activity was developed by supporting the analysis of data obtained through laboratory measurements from a careful study of Failure Analysis (FA).","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133292489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-12DOI: 10.1109/IOLTS56730.2022.9897289
Tiziano Fiorucci, G. D. Natale, J. Daveau, P. Roche
In the context of functional verification, the focus has always been on hardware and its ability to be both resilient to errors and to recover from them autonomously. In order to evaluate these characteristics, an extensive use of Fault Injection tools is made to achieve clear and granular results. These testing campaigns are carried out on the entire DUT and require a consistent amount of time and computational resources. The possibility of reducing these costs applying modern techniques as the study of the Dysfunctional State Machine or the proof of concept regarding the composability of single block fault injection campaigns to obtain a library of component of which the reliability metrics are well known, as already been extensively discussed and proven on hardware. In this work instead the application of this methodologies to software is presented for the first time. In order to do so, the software has been divided into basic block, atomic chunks of code having precise carachteristics that will ensure the possibility to study them singularly and then recompose them into a software product which reliability metrics are known, without the need for complete Fault injection campaign.
{"title":"Software Product Reliability Based on Basic Block Metrics Recomposition","authors":"Tiziano Fiorucci, G. D. Natale, J. Daveau, P. Roche","doi":"10.1109/IOLTS56730.2022.9897289","DOIUrl":"https://doi.org/10.1109/IOLTS56730.2022.9897289","url":null,"abstract":"In the context of functional verification, the focus has always been on hardware and its ability to be both resilient to errors and to recover from them autonomously. In order to evaluate these characteristics, an extensive use of Fault Injection tools is made to achieve clear and granular results. These testing campaigns are carried out on the entire DUT and require a consistent amount of time and computational resources. The possibility of reducing these costs applying modern techniques as the study of the Dysfunctional State Machine or the proof of concept regarding the composability of single block fault injection campaigns to obtain a library of component of which the reliability metrics are well known, as already been extensively discussed and proven on hardware. In this work instead the application of this methodologies to software is presented for the first time. In order to do so, the software has been divided into basic block, atomic chunks of code having precise carachteristics that will ensure the possibility to study them singularly and then recompose them into a software product which reliability metrics are known, without the need for complete Fault injection campaign.","PeriodicalId":274595,"journal":{"name":"2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130859199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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