Silicon Debug and DFT for SOC IP

Abstract

Nanometer circuits and fabrication process both are becoming increasingly complex at the same time. The very nature of silicon defects continue to evolve with these ground shift and are now focused on timing, signal integrity and process variations [1]. It is not enough to simply have full scan ATPG vectors. There will be diagnostics built into the ATPG tools to fall back on when the ATPG tests fail, but these don't help debug timing defects and when the fail test data is compressed [2]. When yields fall and there is a danger to miss the TTM, TTP, TTx windows, the SOC integrator must be ready for quick debug. Silicon Debug has evolved to be a process that requires planning, tools, and engineering resources. The basic DFT principles of controllability and observability need to be extended to isolate a failing IP. Last but not the least, both SOC IP provider and integrator need to support diagnostics or Failure Analysis to zero-in on a defect. Nanometer fails require a paradigm shift, from Design ¿ for-Test to Design-for-Debug. This tutorial will help the attendees recognize, enjoin and improve the Debug paradigm.