Instruction set extension and hardware acceleration for SVM application toward a vector processor

Abstract

This paper presents instruction set extension and hardware acceleration for SVM application toward a vector processor. Based on the nyuzi processor, we customize the corresponding hardware acceleration unit, namely, kernel function processing unit (KPU), both supporting the linear kernel function and radial basis function (RBF) kernel. This work we utilize the mask vector to realize the exponential computation, and the total RBF kernel is completed with only approximately 35 basic instructions. The design is synthesized with SMIC 65nm CMOS technology, requiring 887 equivalent kGates and the max frequency is 540MHz. The simulation results show that with KPU the cycles of SVM training is obviously decreased and speedup is 2.62.