The 3D modeling and SI/PI co-sim analysis for mixed-referenced high speed GDDR5

Abstract

In this paper, a methodology for combined simulation (co-sim) of power and signal to ensure a proper signal-to-power-ground ratio in vertical connections is presented. Capturing the vertical return current, power-to-signal, and signal-to-signal crosstalk simultaneously and accurately requires the modeling of the entire memory channel using 3D tools. Combined simulations allow a highly sensitive analysis in the design of vertical return path such as plated-through-hole (PTH) and ball grid array (BGA) connections. Proposed co-sim methodology is demonstrated with GDDR5 memory channel simulations based on two validation boards with a throughput-computing, high-performance processor. As a result of the analysis, design guidelines and recommendations were defined.