B. Moon, D. Jung, J. Chung, C. Joung, J. Hong, S. Lee, Y. Shin, C. Yoo
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引用次数: 2
Abstract
A full-digital 12-channel, 100-step capacitive sensor is described. The capacitance to be sensed forms an RC-delay line whose delay is compared with that of a reference RC-delay line. The difference of the RC delays is sensed by a simple full-digital time-to-digital converter (TDC). By compensating the parasitic capacitance at power up, the capacitive sensor implemented in a 0.35 mum standard digital CMOS technology shows 30fF sensing resolution. The capacitive sensor consumes 5 muA per channel under 3.3V supply voltage.
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