T. Sueyoshi, H. Uchida, H.J. Mattausch, T. Koide, Y. Mitani, T. Hironaka
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引用次数: 1
Abstract
We designed a compact, high-speed, and low-power hank-type 12-port register file test chip for highly-parallel processors in 0.35μm CMOS technology. In this full-custom test chip design, 72% smaller area, 25% shorter access cycle time, and 62% lower power consumption are achieved in comparison to the conventional 12-port-cell-based register file.
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