Pub Date : 2004-10-04DOI: 10.1109/ASPDAC.2004.1337537
Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang
We address the practical problem of fixed-outline VLSI floorplanning with minimizing the objective of area. This problem was shown significantly much more difficult than the well-researched floorplan problems without fixed-outline regime (N. Saurabh, et al. (2001)). We successfully develop an algorithm with evolutionary search to efficiently handle the fixed-die floorplanning problem and achieve near 100% successful probability, on the average.
{"title":"Fixed-outline floorplanning through evolutionary search","authors":"Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang","doi":"10.1109/ASPDAC.2004.1337537","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337537","url":null,"abstract":"We address the practical problem of fixed-outline VLSI floorplanning with minimizing the objective of area. This problem was shown significantly much more difficult than the well-researched floorplan problems without fixed-outline regime (N. Saurabh, et al. (2001)). We successfully develop an algorithm with evolutionary search to efficiently handle the fixed-die floorplanning problem and achieve near 100% successful probability, on the average.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114189010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337565
N. Chabini, W. Wolf
The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address this problem in the case of synchronous sequential digital designs, one needs to move some registers while applying voltage scaling. Moving these registers shifts some computational elements from critical paths, and can be done by basic retiming. Integrating basic retiming and voltage scaling to address this NP-hard problem cannot in general be done in polynomial run-time. We propose to first apply a guided retiming and then to apply supply voltage scaling on the retimed design. We devise new polynomial time algorithms to realize this guided retiming, and the supply voltage scaling on the retimed design. Experimental results on known benchmarks have shown that the proposed approach can reduce dynamic power consumption by factors as high as 61% for single-phase designs with minimal clock period. Also, they have shown that it can solve optimally the problem, and produce converter-free designs with reduced dynamic power consumption. For large size circuits from ISCAS'89 benchmark suite, the proposed algorithms run in 15s-1h.
{"title":"An approach for reducing dynamic power consumption in synchronous sequential digital designs","authors":"N. Chabini, W. Wolf","doi":"10.1109/ASPDAC.2004.1337565","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337565","url":null,"abstract":"The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address this problem in the case of synchronous sequential digital designs, one needs to move some registers while applying voltage scaling. Moving these registers shifts some computational elements from critical paths, and can be done by basic retiming. Integrating basic retiming and voltage scaling to address this NP-hard problem cannot in general be done in polynomial run-time. We propose to first apply a guided retiming and then to apply supply voltage scaling on the retimed design. We devise new polynomial time algorithms to realize this guided retiming, and the supply voltage scaling on the retimed design. Experimental results on known benchmarks have shown that the proposed approach can reduce dynamic power consumption by factors as high as 61% for single-phase designs with minimal clock period. Also, they have shown that it can solve optimally the problem, and produce converter-free designs with reduced dynamic power consumption. For large size circuits from ISCAS'89 benchmark suite, the proposed algorithms run in 15s-1h.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123101551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337579
Zhong Wang, Jianwen Zhu
While fast timing analysis methods based on model order reduction have been well established for linear circuits, the timing analysis for nonlinear circuits, which are dominant in digital circuits, is usually performed by a SPICE-like, numerical integration-based approach solving differential equations. We propose a new technique that leads to the transient solution of charge/discharge paths with a complexity equivalent to only K DC operating point calculations, where K is the number of transistors along the path. This is accomplished by approximating each nodal voltage as a piecewise quadratic waveform, whose characteristics can be determined by matching the charge/discharge currents calculated by the capacitive components and the resistive components. Successive chord method is then applied to reduce the matrix construction and inversion overhead. Experiments on a wide range of circuits show that an average of 20 times speed-up over HSPICE simulation (transient time only) with 10 picosecond step size can be achieved, while maintaining an average accuracy of 98.03%.
{"title":"Piecewise quadratic waveform matching with successive chord iteration","authors":"Zhong Wang, Jianwen Zhu","doi":"10.1109/ASPDAC.2004.1337579","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337579","url":null,"abstract":"While fast timing analysis methods based on model order reduction have been well established for linear circuits, the timing analysis for nonlinear circuits, which are dominant in digital circuits, is usually performed by a SPICE-like, numerical integration-based approach solving differential equations. We propose a new technique that leads to the transient solution of charge/discharge paths with a complexity equivalent to only K DC operating point calculations, where K is the number of transistors along the path. This is accomplished by approximating each nodal voltage as a piecewise quadratic waveform, whose characteristics can be determined by matching the charge/discharge currents calculated by the capacitive components and the resistive components. Successive chord method is then applied to reduce the matrix construction and inversion overhead. Experiments on a wide range of circuits show that an average of 20 times speed-up over HSPICE simulation (transient time only) with 10 picosecond step size can be achieved, while maintaining an average accuracy of 98.03%.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116685134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital circuits from software designs and formal executable specifications can be automatically synthesized using hardware compilation or 'C based logic synthesis'. Designs can be verified using that same formal specification and coupled with the increasing deployment of higher-level C based languages and IP reuse in hardware design and system codesign, C based logic synthesis is enabling new methodologies and levels of designer productivity. We discuss the rationale for such a synthesis approach, the required semantics and compilation technology and offer a contrast with RTL synthesis. Design examples are used to provide case studies of practical experience.
{"title":"Using C based logic synthesis to bridge the productivity gap","authors":"C. Sullivan, Alex Wilson, S. Chappell","doi":"10.5555/1015090.1015178","DOIUrl":"https://doi.org/10.5555/1015090.1015178","url":null,"abstract":"Digital circuits from software designs and formal executable specifications can be automatically synthesized using hardware compilation or 'C based logic synthesis'. Designs can be verified using that same formal specification and coupled with the increasing deployment of higher-level C based languages and IP reuse in hardware design and system codesign, C based logic synthesis is enabling new methodologies and levels of designer productivity. We discuss the rationale for such a synthesis approach, the required semantics and compilation technology and offer a contrast with RTL synthesis. Design examples are used to provide case studies of practical experience.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126137919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337620
Haobo Yu, R. Dömer, D. Gajski
To meet the challenge of increasing design complexity, designers are turning to system level design languages (SLDLs) to model systems at a higher level of abstraction. We present a method of automatically generating embedded software from system specification written in SLDL. Several refinement steps and intermediate models are introduced in our software generation flow. We demonstrate the effectiveness of the proposed method by a tool which can generate efficient ANSI C code from system models written in SLDL.
{"title":"Embedded software generation from system level design languages","authors":"Haobo Yu, R. Dömer, D. Gajski","doi":"10.1109/ASPDAC.2004.1337620","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337620","url":null,"abstract":"To meet the challenge of increasing design complexity, designers are turning to system level design languages (SLDLs) to model systems at a higher level of abstraction. We present a method of automatically generating embedded software from system specification written in SLDL. Several refinement steps and intermediate models are introduced in our software generation flow. We demonstrate the effectiveness of the proposed method by a tool which can generate efficient ANSI C code from system models written in SLDL.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123288387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337582
K. Min, Young-Hee Kim, D. Kim, Dong Myeong Kim, Jin-Hong Ahn
A new CMOS large-current-output positive pump is proposed and compared with the conventional pump. In this new pump scheme, two auxiliary pumps which are driven by nonoverlapping clocks control the transfer and precharge switches, respectively, increasing the 'ON' conductance of the transfer switches very much at sub-1-V-V/sub DD/ range. The output current improvement of this new pump reaches to 1.6 times larger than the conventional pump with an area penalty less than 10%. This new pump was fabricated in 0.35-/spl mu/m n-well process technology and its effectiveness is firstly verified.
提出了一种新型的CMOS大电流输出正泵，并与传统泵进行了比较。在这个新的泵浦方案中，两个由非重叠时钟驱动的辅助泵分别控制转移开关和预充开关，在sub-1- v - v /sub - DD/范围内大大增加了转移开关的导通。该泵的输出电流比传统泵提高1.6倍，面积损失小于10%。该泵以0.35-/spl mu/m n井工艺制造，并首次验证了其有效性。
{"title":"A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications","authors":"K. Min, Young-Hee Kim, D. Kim, Dong Myeong Kim, Jin-Hong Ahn","doi":"10.1109/ASPDAC.2004.1337582","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337582","url":null,"abstract":"A new CMOS large-current-output positive pump is proposed and compared with the conventional pump. In this new pump scheme, two auxiliary pumps which are driven by nonoverlapping clocks control the transfer and precharge switches, respectively, increasing the 'ON' conductance of the transfer switches very much at sub-1-V-V/sub DD/ range. The output current improvement of this new pump reaches to 1.6 times larger than the conventional pump with an area penalty less than 10%. This new pump was fabricated in 0.35-/spl mu/m n-well process technology and its effectiveness is firstly verified.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129781128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337674
B. Gorjiara, P. Chou, N. Bagherzadeh, Mehrdad Reshadi, D. W. Jensen
To minimize energy consumption by voltage scaling in design of heterogeneous real-time embedded systems, it is necessary to perfom two distinct tasks: task scheduling (TS) and voltage selection (VS). Techniques propased to date either are fast hut yield inetlicient results, or output efficient solutions after many slow iterations. As a core problem to solve in the inner Iwp of a system-level optimization cycle, it is critical that the algorithm he fast while producing high quality results. This paper presents a new technique called EvolutioMry Relative Slack Distribution Voltage Scheduling (ERSD-VS) that achieves both speed and etrciency. It addresses priority adjustment and slack distribution issues with low cost heuristics. Experimental results from running publicly available testhenches show up to 42% energy saving compared to a published technique called EVEN-VS. It also shows up to 70 times speed improvement compared to an efficient technique called EE-GLSA.
{"title":"Fast and efficient voltage scheduling by evolutionary slack distribution","authors":"B. Gorjiara, P. Chou, N. Bagherzadeh, Mehrdad Reshadi, D. W. Jensen","doi":"10.1109/ASPDAC.2004.1337674","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337674","url":null,"abstract":"To minimize energy consumption by voltage scaling in design of heterogeneous real-time embedded systems, it is necessary to perfom two distinct tasks: task scheduling (TS) and voltage selection (VS). Techniques propased to date either are fast hut yield inetlicient results, or output efficient solutions after many slow iterations. As a core problem to solve in the inner Iwp of a system-level optimization cycle, it is critical that the algorithm he fast while producing high quality results. This paper presents a new technique called EvolutioMry Relative Slack Distribution Voltage Scheduling (ERSD-VS) that achieves both speed and etrciency. It addresses priority adjustment and slack distribution issues with low cost heuristics. Experimental results from running publicly available testhenches show up to 42% energy saving compared to a published technique called EVEN-VS. It also shows up to 70 times speed improvement compared to an efficient technique called EE-GLSA.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128315013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337650
A. Balasundaram, A. Pereira, Jun-Cheol Park, V. Mooney
This paper presents a high speed VLSI implementation of wavelet and golay error control codes. The design has been fabricated by MOSIS in a TMSC 0.25 μm CMOS process. Experimental results show a maximum speed of 145 MHz and a data transfer rate of 870 Mb/sec.
{"title":"Golay and wavelet error control codes in VLSI","authors":"A. Balasundaram, A. Pereira, Jun-Cheol Park, V. Mooney","doi":"10.1109/ASPDAC.2004.1337650","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337650","url":null,"abstract":"This paper presents a high speed VLSI implementation of wavelet and golay error control codes. The design has been fabricated by MOSIS in a TMSC 0.25 μm CMOS process. Experimental results show a maximum speed of 145 MHz and a data transfer rate of 870 Mb/sec.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123496920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337604
G. Surendra, Subhasish Banerjee, S. Nandy
We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are normally delayed in the issue stage due to resource constraints even though their data dependencies are satisfied. Issuing ROD instructions earlier than normal and executing them on slow functional units to obtain power benefits reduce these delays. This scheme achieves around 6% to 8% power reduction with average performance degradation of about 2%. Alternatively, instead of reducing the delays faced by instructions in the pipeline, increasing them by deliberately stalling certain instructions at appropriate times minimizes the duration for which the processor is underutilized leading to 2.5-4% power savings with less than 0.3% performance degradation.
{"title":"Power-performance trade-off using pipeline delays","authors":"G. Surendra, Subhasish Banerjee, S. Nandy","doi":"10.1109/ASPDAC.2004.1337604","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337604","url":null,"abstract":"We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are normally delayed in the issue stage due to resource constraints even though their data dependencies are satisfied. Issuing ROD instructions earlier than normal and executing them on slow functional units to obtain power benefits reduce these delays. This scheme achieves around 6% to 8% power reduction with average performance degradation of about 2%. Alternatively, instead of reducing the delays faced by instructions in the pipeline, increasing them by deliberately stalling certain instructions at appropriate times minimizes the duration for which the processor is underutilized leading to 2.5-4% power savings with less than 0.3% performance degradation.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-27DOI: 10.1109/ASPDAC.2004.1337535
J. Minz, S. Lim
The routing environment for the new emerging mixed-signal system-on-package (SOP) technology is more advanced than that of the conventional PCB or MCM technology - pins are located at all layers of SOP packaging substrate rather than the top-most layer only. We propose a new interconnect-centric layer assignment algorithm named LA-SOP that handles arbitrary routing topologies and produces near optimal results. The contribution of this work is threefold: (i) modeling of the SOP routing resource, (ii) formulation of the new SOP layer assignment problem, and (iii) development of a fast and novel algorithm that considers the various design constraints unique to SOP. We review various approaches for the PCB, IC and MCM algorithms and investigate their applicability to the SOP model. Our related experimental results demonstrate the effectiveness of our algorithm LA-SOP.
{"title":"Layer assignment for reliable system-on-package","authors":"J. Minz, S. Lim","doi":"10.1109/ASPDAC.2004.1337535","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337535","url":null,"abstract":"The routing environment for the new emerging mixed-signal system-on-package (SOP) technology is more advanced than that of the conventional PCB or MCM technology - pins are located at all layers of SOP packaging substrate rather than the top-most layer only. We propose a new interconnect-centric layer assignment algorithm named LA-SOP that handles arbitrary routing topologies and produces near optimal results. The contribution of this work is threefold: (i) modeling of the SOP routing resource, (ii) formulation of the new SOP layer assignment problem, and (iii) development of a fast and novel algorithm that considers the various design constraints unique to SOP. We review various approaches for the PCB, IC and MCM algorithms and investigate their applicability to the SOP model. Our related experimental results demonstrate the effectiveness of our algorithm LA-SOP.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"2 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131348739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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