{"title":"A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000","authors":"Xin Zhao, A. Erdogan, T. Arslan","doi":"10.1109/SOCCON.2009.5398095","DOIUrl":null,"url":null,"abstract":"In this paper, we present a novel Context Modeling (CM) architecture used in JPEG2000 encoder targeting next generation of cameras. The implementation is based on a newly emerging coarsegrained Dynamically Reconfigurable (DR) processor. A novel partial parallel architecture for the CM is introduced which can be easily tailored for the target DR processor in order to achieve higher performance results. Simulation results show that the resulting architecture provides throughput reaching up to 60.82MS/s, representing 1.2x speed up compared to previous parallel CM architectures.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International SOC Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCCON.2009.5398095","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, we present a novel Context Modeling (CM) architecture used in JPEG2000 encoder targeting next generation of cameras. The implementation is based on a newly emerging coarsegrained Dynamically Reconfigurable (DR) processor. A novel partial parallel architecture for the CM is introduced which can be easily tailored for the target DR processor in order to achieve higher performance results. Simulation results show that the resulting architecture provides throughput reaching up to 60.82MS/s, representing 1.2x speed up compared to previous parallel CM architectures.
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