Optimal motion estimation using reduced bits and its low power VLSI implementation

Abstract

Full search Motion Estimation (M.E.) process is computationally intensive and power consuming, which might be unsuitable for battery powered real time applications. In this work, different M.E. algorithms are being presented. Algorithms 1 to 3 are beneficial for low power and high throughput VLSI implementation while keeping the quality at optimum level. Three VLSI architectures are presented corresponding to the three algorithms. Theoretically, Architecture 1 reduces the pixel accesses from memory and hence power consumption by 23%. Architecture 2 reduces the pixel accesses by 48% and Architecture 3 reduces pixel accesses by 52%. Finally we present a suboptimal fast M.E. algorithm which is a modified form of Diamond Search algorithm, has less complexity and improved quality as compared to standard diamond search M.E. algorithm.