An effective routing methodology in the era of 0.2 /spl mu/m and beyond technologies for reducing the DRAM design cost

Abstract

The optimum routing methodology for high-performance and fast-layout time DRAM design in the era beyond 0.2 /spl mu/m technology is investigated. The key attributes of the methodology are that it does pitch-based interconnect design (/spl lambda/-rule) and then analyzes the signal integrity through hierarchical interconnect modeling. The final goal of this work is to make the CAD tool for designing the IP-based logic blocks with interconnect net modeling instead of feature-based interconnect parasitic modeling.